ENTITY dp_mux_x2 IS
PORT (
  sel0	: in  BIT;
  sel1	: in  BIT;
  i0	: in  BIT;
  i1	: in  BIT;
  q	: out BIT;
  vdd	: in  BIT;
  vss	: in  BIT
);
END dp_mux_x2;

ARCHITECTURE vbe OF dp_mux_x2 IS

BEGIN
  ASSERT (vdd and not vss)
  REPORT "power supply is missing on dp_mux_x2"
  SEVERITY WARNING;

  ASSERT (sel0 xor sel1)
  REPORT "wrong control signals on dp_mux_x2"
  SEVERITY WARNING;

  q <= (sel0 and i0) or (sel1 and i1);

END;