ENTITY dp_ts_x4 IS
PORT (
  enx	 : in  BIT;
  nenx	 : in  BIT;
  i	 : in  BIT;
  q	 : out MUX_BIT BUS;
  vdd	 : in  BIT;
  vss	 : in  BIT
);
END dp_ts_x4;

ARCHITECTURE vbe OF dp_ts_x4 IS

BEGIN
  ASSERT (vdd and not vss)
  REPORT "power supply is missing on dp_ts_x4"
  SEVERITY WARNING;

  ASSERT (enx xor  nenx)
  REPORT "wrong control signals on dp_ts_x4"
  SEVERITY WARNING;

  label0 : BLOCK (enx = '1')
  BEGIN
    q <= GUARDED i;
  END BLOCK label0;

END;