ENTITY rf_fifo_clock IS
PORT (
  ck     : in  BIT;
  wok    : in  BIT;
  cks 	 : inout BIT;
  ckm 	 : inout BIT;
  ckok   : out BIT;
  vdd	 : in  BIT;
  vss	 : in  BIT
);
END rf_fifo_clock;

ARCHITECTURE VBE OF rf_fifo_clock IS

  SIGNAL nck    : BIT;
  SIGNAL sck    : BIT;
  SIGNAL mck    : BIT;
  SIGNAL nsck   : BIT;
  SIGNAL nmck   : BIT;

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on rf_fifo_clock"
  SEVERITY WARNING;

  nck  <= not ck;
  sck  <= nck nor ckm;
  mck  <=  ck nor cks;
  nmck <=  not mck;
  nsck <=  not sck;
  cks  <=  not nsck;
  ckm  <=  not nmck;
  ckok <= mck nand wok;

--      cks <= not(ck);
--	ckm <= ck;
--	ckok <= ckm nand wok;

END;