ENTITY rf_fifo_full IS
PORT (
  ckm 	         : in  BIT;
  reset          : in  BIT;
  fullnext 	 : in  BIT;
  cks            : in  BIT;
  full           : out BIT;
  vdd	         : in  BIT;
  vss	         : in  BIT
);
END rf_fifo_full;

ARCHITECTURE VBE OF rf_fifo_full IS
  SIGNAL latchm	 : REG_BIT REGISTER;
  SIGNAL latchs	 : REG_BIT REGISTER;

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on rf_fifo_full"
  SEVERITY WARNING;

  label0 : BLOCK (ckm = '1')
  BEGIN
    latchm <= GUARDED (fullnext nor reset);
  END BLOCK label0;

  label1 : BLOCK (cks = '1')
  BEGIN
    latchs <= GUARDED (not latchm);
  END BLOCK label1;

  full <= (not latchs);

END;