ENTITY rf_fifo_ptreset IS
PORT (
  nop 	 : in  BIT;
  inc 	 : in  BIT;
  cks    : in  BIT;
  reset  : in  BIT;
  ptm1   : in  BIT;
  pt     : inout BIT;
  vdd	 : in  BIT;
  vss	 : in  BIT
);
END rf_fifo_ptreset;

ARCHITECTURE VBE OF rf_fifo_ptreset IS
  SIGNAL latchm	 : REG_BIT REGISTER;
  SIGNAL latchs	 : REG_BIT REGISTER;
  SIGNAL ckmux     : BIT;

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on rf_fifo_ptreset"
  SEVERITY WARNING;

  ckmux <= nop or inc or reset;
  
  label0 : BLOCK (nop = '1')
  BEGIN
    latchm <= GUARDED pt;
  END BLOCK label0;

  label1 : BLOCK (inc = '1')
  BEGIN
    latchm <= GUARDED ptm1;
  END BLOCK label1;

  label2 : BLOCK (reset = '1')
  BEGIN
    latchm <= GUARDED '0';
  END BLOCK label2;

  labels : BLOCK (cks = '1')
  BEGIN
    latchs <= GUARDED (not latchm);
  END BLOCK labels;

  pt <= (not latchs);

END;