BuYTgT'30-OCT-99-20:16:11 30-OCT-99-20:16:11 (30-OCT-9920:16:117.0 version of GHDL! VSS $WD1ACTION[1:1]VDDA2_X2"$WD1ACTION$1TEMPS0 QI0I1  INPUT  INPUT WIRESUPPLY1SUPPLY0) * Circuit a2_x2 ( Input i0 , Input i1 , Output q , Supply1 vdd , Supply0 vss ); WIRE q := (i0 and i1) ; EndCircuit N&30-OCT-99-20:16:11 30-OCT-99-20:16:11TTL090CIRCUIT\10 Symbols 1 Elements 5 Carriers 13 Objects 5 Terminals 1 Action lists 1 Actions 0 RamRoms I0 1 I1 1 Q 4 VDD 8 VSS 7 30-OCT-99-20:16:11 30-OCT-99-20:16:11 1 7 1 2