--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY ts_x4 IS
PORT(
  cmd	: IN STD_LOGIC;
  i	: IN STD_LOGIC;
  q	: OUT STD_LOGIC
);
END ts_x4;

ARCHITECTURE RTL OF ts_x4 IS
BEGIN
  PROCESS ( i, cmd )
  BEGIN
    IF (cmd = '1')
    THEN q <= i;
    ELSE q <= 'Z';
    END IF;
  END PROCESS;
END RTL;