ENTITY circuit is PORT ( ck : in BIT; jour : in BIT; reset : in BIT; vdd : in BIT; vss : in BIT; i : in BIT_VECTOR(3 DOWNTO 0); porte : out BIT; alarm : out BIT ); END circuit; ARCHITECTURE MOORE OF circuit is TYPE ETAT_TYPE IS (E0, E1, E2, E3, E4, E5, EA); SIGNAL EF, CS : ETAT_TYPE; CONSTANT digit0 : BIT_VECTOR (3 DOWNTO 0) := B"1111" ; -- O CONSTANT digit1 : BIT_VECTOR (3 DOWNTO 0) := B"0101" ; -- 5 CONSTANT digit2 : BIT_VECTOR (3 DOWNTO 0) := B"0011" ; -- 3 CONSTANT digit3 : BIT_VECTOR (3 DOWNTO 0) := B"1100" ; -- A CONSTANT digit4 : BIT_VECTOR (3 DOWNTO 0) := B"0001" ; -- 1 CONSTANT digit5 : BIT_VECTOR (3 DOWNTO 0) := B"0111" ; -- 7 --PRAGMA CURRENT_STATE CS --PRAGMA NEXT_STATE EF --PRAGMA CLOCK ck --PRAGMA FIRST_STATE E0 BEGIN PROCESS ( CS, i) BEGIN IF ( reset = '1' ) THEN EF <= E0; porte <= '0'; alarm <= '0'; ELSE CASE CS is WHEN E0 => porte <= '0'; alarm <= '0'; IF ( i = digit0 ) THEN IF ( jour = '1' ) THEN EF <= E5; ELSE EF <= EA; END IF; ELSE IF ( i = digit1 ) THEN EF <= E1; ELSE IF ( jour = '1' ) THEN EF <= E0; ELSE EF <= EA; END IF; END IF; END IF; WHEN E1 => porte <= '0'; alarm <= '0'; IF ( i = digit2 ) THEN EF <= E2; ELSE IF ( jour = '1' ) THEN EF <= E0; ELSE EF <= EA; END IF; END IF; WHEN E2 => porte <= '0'; alarm <= '0'; IF ( i = digit3 ) THEN EF <= E3; ELSE IF ( jour = '1' ) THEN EF <= E0; ELSE EF <= EA; END IF; END IF; WHEN E3 => porte <= '0'; alarm <= '0'; IF ( i = digit4 ) THEN EF <= E4; ELSE IF ( jour = '1' ) THEN EF <= E0; ELSE EF <= EA; END IF; END IF; WHEN E4 => porte <= '0'; alarm <= '0'; IF ( i = digit5 ) THEN EF <= E5; ELSE IF ( jour = '1' ) THEN EF <= E0; ELSE EF <= EA; END IF; END IF; WHEN E5 => porte <= '1'; alarm <= '0'; EF <= E5; WHEN EA => porte <= '0'; alarm <= '1'; EF <= EA; END CASE; END IF; END PROCESS; PROCESS( ck ) BEGIN IF ( ck = '1' AND NOT ck'STABLE ) THEN CS <= EF; END IF; END PROCESS; END MOORE;