-------------------------------------------------------------- -- Structural description if the DLXm chip -- -- instantiating core and symbolic pads -- -- input symbolic pads done -- -- modif plot ck -- modif chemin de test -- scin : datapath --> control : scout -- control scin : sequencer --> status: scout -- modif byte (0 to 3) pour conformite a la carte et sortie non inversee -- modif rw non inverse -- datain_dpt : plot non inverse -- dataout_dpt : plot non inverse -- rw_ctl : ctl plot tristate data non inverse -- frz_ctl : ctl plot tristate adresse non inverse -- adr : plot non inverse -- 2 horloeges ck_ctl vers le controle et ck_dpr vers le datapath -- version v0.2 -- -- January 1995 -- --------------------------------------------------------------- ENTITY mips_chip IS PORT ( ck : in bit; -- external clock reset : in bit; -- external reset frz : in bit; -- freeze int : in bit_vector(5 downto 0); -- external interrupts data : inout mux_vector(31 downto 0) bus; -- inout data W : out bit_vector(0 to 1); -- select data byte rw : out bit; -- read or write berr : in bit; -- bus error adr : out mux_vector(31 downto 0) bus; -- address word scin : in bit; -- scan in test : in bit; -- test mode scout : out bit; -- scan out vdd : in bit; -- core supply vss : in bit; -- core supply vddp : in bit; -- pad supply vssp : in bit -- pad supply ); END mips_chip; ARCHITECTURE structural_view OF mips_chip IS COMPONENT mips_core port ( adr : out BIT_VECTOR(31 DOWNTO 0); datain : in BIT_VECTOR(31 DOWNTO 0); dataout : out BIT_VECTOR(31 DOWNTO 0); int : in BIT_VECTOR(5 DOWNTO 0); scin : in BIT; scout : out BIT; test : in BIT; reset : in BIT; frz : in BIT; W : out BIT_VECTOR(0 to 1); rw : out BIT; berr : in BIT; rw_ctl : out BIT_VECTOR(15 downto 0); frz_ctl : out BIT_VECTOR(15 downto 0); ck_ctl : in BIT; ck_dpt : in BIT; vdd : in BIT; vss : in BIT ); END COMPONENT; COMPONENT piot_sp port ( i : in BIT; b : in BIT; t : out BIT; pad : inout MUX_BIT bus; ck : in BIT; vdde : in BIT; vddi : in BIT; vsse : in BIT; vssi : in BIT ); END COMPONENT; COMPONENT pot_sp port ( i : in BIT; b : in BIT; pad : out MUX_BIT BUS; ck : in BIT; vdde : in BIT; vddi : in BIT; vsse : in BIT; vssi : in BIT ); END COMPONENT; COMPONENT po_sp port ( i : in BIT; pad : out BIT; ck : in BIT; vdde : in BIT; vddi : in BIT; vsse : in BIT; vssi : in BIT ); END COMPONENT; COMPONENT pi_sp port ( pad : in BIT; t : out BIT; ck : in BIT; vdde : in BIT; vddi : in BIT; vsse : in BIT; vssi : in BIT ); END COMPONENT; COMPONENT pck_sp port ( pad : in BIT; ck : out BIT; vdde : in BIT; vddi : in BIT; vsse : in BIT; vssi : in BIT ); END COMPONENT; COMPONENT pvddi_sp port ( ck : in BIT; vdde : in BIT; vddi : in BIT; vsse : in BIT; vssi : in BIT ); END COMPONENT; COMPONENT pvssick_sp port ( cko : out WOR_BIT BUS; ck : in BIT; vdde : in BIT; vddi : in BIT; vsse : in BIT; vssi : in BIT ); END COMPONENT; COMPONENT pvssi_sp port ( ck : in BIT; vdde : in BIT; vddi : in BIT; vsse : in BIT; vssi : in BIT ); END COMPONENT; COMPONENT pvdde_sp port ( ck : in BIT; vdde : in BIT; vddi : in BIT; vsse : in BIT; vssi : in BIT ); END COMPONENT; COMPONENT pvsse_sp port ( ck : in BIT; vdde : in BIT; vddi : in BIT; vsse : in BIT; vssi : in BIT ); END COMPONENT; COMPONENT pvsseck_sp port ( cko : out WOR_BIT BUS; ck : in BIT; vdde : in BIT; vddi : in BIT; vsse : in BIT; vssi : in BIT ); END COMPONENT; SIGNAL ck_ctl_c : bit; -- core clock SIGNAL ck_dpt_c : bit; -- core clock SIGNAL frz_c : bit; SIGNAL int_c : bit_vector(5 downto 0); SIGNAL adr_c : bit_vector(31 downto 0); -- core address signal SIGNAL W_c : bit_vector(0 to 1); SIGNAL datain_c : bit_vector(31 downto 0); SIGNAL dataout_c : bit_vector(31 downto 0); SIGNAL rw_c : bit; SIGNAL berr_c : bit; SIGNAL scout_c : bit; SIGNAL reset_c : bit; SIGNAL rw_ctl_c : bit_vector(15 downto 0); -- data tristate control SIGNAL frz_ctl_c : bit_vector(15 downto 0); -- address tristate control SIGNAL scin_c : bit; SIGNAL test_c : bit; SIGNAL ck_ring : bit; -- pad ring clock BEGIN core : mips_core PORT MAP ( vss => vss, -- core supply vdd => vdd, -- core supply ck_ctl => ck_ctl_c, -- core control clock ck_dpt => ck_dpt_c, -- core dpt clock rw_ctl => rw_ctl_c, -- inout data cntrol frz_ctl => frz_ctl_c, -- out address control rw => rw_c, W => W_c, berr => berr_c, frz => frz_c, reset => reset_c, test => test_c, scout => scout_c, scin => scin_c, int => int_c, dataout => dataout_c, datain => datain_c, adr => adr_c ); clock_ring : pck_sp PORT MAP ( pad => ck, ck => ck_ring, vdde => vddp, vddi => vdd, vsse => vssp, vssi => vss); ad_out_pl0 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(0), b => frz_ctl_c(0), i => adr_c(0)); ad_out_pl1 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(1), b => frz_ctl_c(0), i => adr_c(1)); ad_out_pl2 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(2), b => frz_ctl_c(1), i => adr_c(2)); ad_out_pl3 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(3), b => frz_ctl_c(1), i => adr_c(3)); ad_out_pl4 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(4), b => frz_ctl_c(2), i => adr_c(4)); ad_out_pl5 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(5), b => frz_ctl_c(2), i => adr_c(5)); ad_out_pl6 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(6), b => frz_ctl_c(3), i => adr_c(6)); ad_out_pl7 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(7), b => frz_ctl_c(3), i => adr_c(7)); ad_out_pl8 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(8), b => frz_ctl_c(4), i => adr_c(8)); ad_out_pl9 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(9), b => frz_ctl_c(4), i => adr_c(9)); ad_out_pl10 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(10), b => frz_ctl_c(5), i => adr_c(10)); ad_out_pl11 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(11), b => frz_ctl_c(5), i => adr_c(11)); ad_out_pl12 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(12), b => frz_ctl_c(6), i => adr_c(12)); ad_out_pl13 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(13), b => frz_ctl_c(6), i => adr_c(13)); ad_out_pl14 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(14), b => frz_ctl_c(7), i => adr_c(14)); ad_out_pl15 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(15), b => frz_ctl_c(7), i => adr_c(15)); ad_out_pl16 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(16), b => frz_ctl_c(8), i => adr_c(16)); ad_out_pl17 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(17), b => frz_ctl_c(8), i => adr_c(17)); ad_out_pl18 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(18), b => frz_ctl_c(9), i => adr_c(18)); ad_out_pl19 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(19), b => frz_ctl_c(9), i => adr_c(19)); ad_out_pl20 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(20), b => frz_ctl_c(10), i => adr_c(20)); ad_out_pl21 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(21), b => frz_ctl_c(10), i => adr_c(21)); ad_out_pl22 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(22), b => frz_ctl_c(11), i => adr_c(22)); ad_out_pl23 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(23), b => frz_ctl_c(11), i => adr_c(23)); ad_out_pl24 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(24), b => frz_ctl_c(12), i => adr_c(24)); ad_out_pl25 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(25), b => frz_ctl_c(12), i => adr_c(25)); ad_out_pl26 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(26), b => frz_ctl_c(13), i => adr_c(26)); ad_out_pl27 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(27), b => frz_ctl_c(13), i => adr_c(27)); ad_out_pl28 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(28), b => frz_ctl_c(14), i => adr_c(28)); ad_out_pl29 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(29), b => frz_ctl_c(14), i => adr_c(29)); ad_out_pl30 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(30), b => frz_ctl_c(15), i => adr_c(30)); ad_out_pl31 : pot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => adr(31), b => frz_ctl_c(15), i => adr_c(31)); dat_inout_pl0 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(0), t => datain_c(0), b => rw_ctl_c(0), i => dataout_c(0)); dat_inout_pl1 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(1), t => datain_c(1), b => rw_ctl_c(0), i => dataout_c(1)); dat_inout_pl2 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(2), t => datain_c(2), b => rw_ctl_c(1), i => dataout_c(2)); dat_inout_pl3 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(3), t => datain_c(3), b => rw_ctl_c(1), i => dataout_c(3)); dat_inout_pl4 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(4), t => datain_c(4), b => rw_ctl_c(2), i => dataout_c(4)); dat_inout_pl5 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(5), t => datain_c(5), b => rw_ctl_c(2), i => dataout_c(5)); dat_inout_pl6 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(6), t => datain_c(6), b => rw_ctl_c(3), i => dataout_c(6)); dat_inout_pl7 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(7), t => datain_c(7), b => rw_ctl_c(3), i => dataout_c(7)); dat_inout_pl8 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(8), t => datain_c(8), b => rw_ctl_c(4), i => dataout_c(8)); dat_inout_pl9 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(9), t => datain_c(9), b => rw_ctl_c(4), i => dataout_c(9)); dat_inout_pl10 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(10), t => datain_c(10), b => rw_ctl_c(5), i => dataout_c(10)); dat_inout_pl11 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(11), t => datain_c(11), b => rw_ctl_c(5), i => dataout_c(11)); dat_inout_pl12 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(12), t => datain_c(12), b => rw_ctl_c(6), i => dataout_c(12)); dat_inout_pl13 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(13), t => datain_c(13), b => rw_ctl_c(6), i => dataout_c(13)); dat_inout_pl14 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(14), t => datain_c(14), b => rw_ctl_c(7), i => dataout_c(14)); dat_inout_pl15 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(15), t => datain_c(15), b => rw_ctl_c(7), i => dataout_c(15)); dat_inout_pl16 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(16), t => datain_c(16), b => rw_ctl_c(8), i => dataout_c(16)); dat_inout_pl17 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(17), t => datain_c(17), b => rw_ctl_c(8), i => dataout_c(17)); dat_inout_pl18 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(18), t => datain_c(18), b => rw_ctl_c(9), i => dataout_c(18)); dat_inout_pl19 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(19), t => datain_c(19), b => rw_ctl_c(9), i => dataout_c(19)); dat_inout_pl20 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(20), t => datain_c(20), b => rw_ctl_c(10), i => dataout_c(20)); dat_inout_pl21 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(21), t => datain_c(21), b => rw_ctl_c(10), i => dataout_c(21)); dat_inout_pl22 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(22), t => datain_c(22), b => rw_ctl_c(11), i => dataout_c(22)); dat_inout_pl23 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(23), t => datain_c(23), b => rw_ctl_c(11), i => dataout_c(23)); dat_inout_pl24 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(24), t => datain_c(24), b => rw_ctl_c(12), i => dataout_c(24)); dat_inout_pl25 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(25), t => datain_c(25), b => rw_ctl_c(12), i => dataout_c(25)); dat_inout_pl26 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(26), t => datain_c(26), b => rw_ctl_c(13), i => dataout_c(26)); dat_inout_pl27 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(27), t => datain_c(27), b => rw_ctl_c(13), i => dataout_c(27)); dat_inout_pl28 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(28), t => datain_c(28), b => rw_ctl_c(14), i => dataout_c(28)); dat_inout_pl29 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(29), t => datain_c(29), b => rw_ctl_c(14), i => dataout_c(29)); dat_inout_pl30 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(30), t => datain_c(30), b => rw_ctl_c(15), i => dataout_c(30)); dat_inout_pl31 : piot_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => data(31), t => datain_c(31), b => rw_ctl_c(15), i => dataout_c(31)); it_in_pl0 : pi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, t => int_c(0), pad => int(0)); it_in_pl1 : pi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, t => int_c(1), pad => int(1)); it_in_pl2 : pi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, t => int_c(2), pad => int(2)); it_in_pl3 : pi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, t => int_c(3), pad => int(3)); it_in_pl4 : pi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, t => int_c(4), pad => int(4)); it_in_pl5 : pi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, t => int_c(5), pad => int(5)); it_in_pl6 : pi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, t => berr_c, pad => berr); scin_pl : pi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, t => scin_c, pad => scin); scout_pl : po_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => scout, i => scout_c); test_pl : pi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, t => test_c, pad => test); reset_pl : pi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, t => reset_c, pad => reset); frz_pl : pi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, t => frz_c, pad => frz); byte_pl0 : po_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => W(0), i => W_c(0)); byte_pl1 : po_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => W(1), i => W_c(1)); rw_pl : po_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp, pad => rw, i => rw_c); vddi_pl_0 : pvddi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp); vddi_pl_1 : pvddi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp); vddi_pl_2 : pvddi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp); vddi_pl_3 : pvddi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp); ck_vssi_pl_3 : pvssick_sp PORT MAP ( cko => ck_dpt_c, ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp); vssi_pl_1 : pvssi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp); vssi_pl_2 : pvssi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp); vssi_pl_0 : pvssi_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vddi => vdd, vdde => vddp); vdde_pl_0 : pvdde_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vdde => vddp, vddi => vdd); vdde_pl_1 : pvdde_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vdde => vddp, vddi => vdd); vdde_pl_2 : pvdde_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vdde => vddp, vddi => vdd); vdde_pl_3 : pvdde_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vdde => vddp, vddi => vdd); vdde_pl_4 : pvdde_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vdde => vddp, vddi => vdd); vdde_pl_5 : pvdde_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vdde => vddp, vddi => vdd); vdde_pl_6 : pvdde_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vdde => vddp, vddi => vdd); vdde_pl_7 : pvdde_sp PORT MAP ( ck => ck_ring, vssi => vss, vsse => vssp, vdde => vddp, vddi => vdd); ck_vsse_pl_0 : pvsseck_sp PORT MAP ( ck => ck_ring, cko => ck_ctl_c, vsse => vssp, vddi => vdd, vdde => vddp, vssi => vss); vsse_pl_1 : pvsse_sp PORT MAP ( ck => ck_ring, vsse => vssp, vddi => vdd, vdde => vddp, vssi => vss); vsse_pl_2 : pvsse_sp PORT MAP ( ck => ck_ring, vsse => vssp, vddi => vdd, vdde => vddp, vssi => vss); vsse_pl_3 : pvsse_sp PORT MAP ( ck => ck_ring, vsse => vssp, vssi => vss, vddi => vdd, vdde => vddp); vsse_pl_4 : pvsse_sp PORT MAP ( ck => ck_ring, vsse => vssp, vssi => vss, vddi => vdd, vdde => vddp); vsse_pl_5 : pvsse_sp PORT MAP ( ck => ck_ring, vsse => vssp, vssi => vss, vddi => vdd, vdde => vddp); vsse_pl_6 : pvsse_sp PORT MAP ( ck => ck_ring, vsse => vssp, vssi => vss, vddi => vdd, vdde => vddp); vsse_pl_7 : pvsse_sp PORT MAP ( ck => ck_ring, vsse => vssp, vssi => vss, vddi => vdd, vdde => vddp); end structural_view;