-- ### -------------------------------------------------------------- ###
-- #									#
-- # file	: mips_cpu.vst						#
-- # date	: september 25 1996						#
-- # version	: v0.2							#
-- # author	: fahim RAHIM					#
-- # descr.	: mips cpu board with on board ram (512 bytes), rom	#
-- #		  (512 bytes = 128 instructions) and, timer		#
-- #									#
-- ### -------------------------------------------------------------- ###

entity mips_cpu is
  port (
       CK       : in    bit                         ;
       TEST     : in    bit                         ;
       SCIN     : in    bit                         ;
       SCOUT    : out   bit                         ;
       RESET    : in    bit                         ;
       FRZ      : in    bit                         ;
       RW       : inout bit                         ;
       W        : inout bit_vector ( 0     to 1)    ;
       DATA     : inout mux_vector (31 downto 0) bus;
       DATA_ADR : inout mux_vector (31 downto 0) bus;
       VDD      : in    bit                         ;
       VSS      : in    bit
       );

end mips_cpu;

architecture structral of mips_cpu is

  signal E_RAMU_N : bit_vector ( 0     to 3)    ;
  signal E_RAMS_N : bit_vector ( 0     to 3)    ;
  signal E_ROMU_N : bit                         ;
  signal E_ROMS_N : bit                         ;
  signal E_TIME_N : bit                         ;
  signal E_ROMR_N : bit				;
  signal E_ROME_N : bit				;

  signal rst      : bit				;
  signal berr     : bit				;
  signal IRQ_N    : bit_vector( 5 downto 0)	;

  component mips_chip
    port ( 
         CK      : in    bit                          ;
         RESET   : in    bit                          ;
         FRZ     : in    bit                          ;
         INT     : in    bit_vector ( 5 downto 0)     ;
         DATA    : inout mux_vector (31 downto 0) bus ;
         W       : out   bit_vector ( 0     to 1)     ;
         RW      : out   bit                          ;
         ADR     : out   mux_vector (31 downto 0) bus ;
         SCIN    : in    bit                          ;
	 BERR    : in    bit			      ;
         TEST    : in    bit                          ;
         SCOUT   : out   bit                          ;
         VDD     : in    bit                          ;
         VSS     : in    bit                          ;
         VDDP    : in    bit                          ;
         VSSP    : in    bit
         ) ;
  end component;

  component mips_dec
    port (
         CK          : in    bit                         ;
         mips_DADR   : in    bit_vector (31 downto 0)    ;
         RW          : in    bit                         ;
         W           : in    bit_vector ( 0     to 1)    ;
	 berr	     : out   bit			 ;
         SEL_ROMU_N  : out   bit                         ;
         SEL_RAMU_N  : out   bit_vector ( 0     to 3)    ;
         SEL_ROMS_N  : out   bit                         ;
         SEL_RAMS_N  : out   bit_vector ( 0     to 3)    ;
         SEL_TIMER_N : out   bit                         ;
         SEL_ROMR_N  : OUT   BIT                         ;
         SEL_ROME_N  : OUT   BIT			 ;
         VDD         : in    bit                         ;
         VSS         : in    bit
         );
  end component;

  component sr64_32a
    port (
         E_N         : in    bit_vector ( 0     to 3)    ;
         W_N         : in    bit                         ;
         DAT         : inout mux_vector (31 downto 0) bus;
         ADR         : in    bit_vector ( 5 downto 0)    ;
         VDD         : in    bit                         ;
         VSS         : in    bit
         );
  end component;

  component romu
    port (
         ADDRESS : in  bit_vector (5  downto 0)    ;
         E_N     : in  bit                         ;
         DATA    : out mux_vector (31 downto 0) bus;
         VDD     : in  bit                         ;
         VSS     : in  bit
         );
  end component;

  component roms
    port (
         ADDRESS : in  bit_vector (5  downto 0)    ;
         E_N     : in  bit                         ;
         DATA    : out mux_vector (31 downto 0) bus;
         VDD     : in  bit                         ;
         VSS     : in  bit
         );
  end component;

 component romr
    port (
         ADDRESS : in  bit_vector (5  downto 0)    ;
         E_N     : in  bit                         ;
         DATA    : out mux_vector (31 downto 0) bus;
         VDD     : in  bit                         ;
         VSS     : in  bit
         );
  end component;

 component rome
    port (
         ADDRESS : in  bit_vector (5  downto 0)    ;
         E_N     : in  bit                         ;
         DATA    : out mux_vector (31 downto 0) bus;
         VDD     : in  bit                         ;
         VSS     : in  bit
         );
  end component;

  component timer
  port (
    CK      : in    bit                         ;	-- external clock
    FRZ     : in    bit                         ;	-- freeze
    RESET_I : in    bit                         ;	-- reset input
    SEL     : in    bit_vector ( 2 downto 0)    ;	-- register selection
    DATA    : inout mux_vector (31 downto 0) bus;	-- data
    RW      : in    bit                         ;	-- access mode
    E_N     : in    bit                         ;	-- chip enable
    RESET_O : out   bit                         ;	-- reset output (= TIMER_RESET OR RESET_I)
    IRQ_N   : out   bit_vector(5 downto 0)	;       -- interrupt request
    VDD     : in    bit                         ;	--
    VSS     : in    bit                         	--
    );
  end component;

begin

  mips1 : mips_chip
    port map (
             INT   => IRQ_N    ,
             TEST  => TEST     ,
             SCIN  => SCIN     ,
             SCOUT => SCOUT    ,
             FRZ   => FRZ      ,
             RESET => RST      ,
             ADR   => DATA_ADR ,
             W     => W        ,
             RW    => RW       ,
             CK    => CK       ,
	     BERR  => BERR     , 
             DATA  => DATA     ,
             VDDP  => VDD      ,
             VSSP  => VSS      ,
             VDD   => VDD      ,
             VSS   => VSS
             );

  mips_dec : mips_dec
    port map (
             CK          => CK       ,
             MIPS_DADR   => DATA_ADR ,
             RW          => RW       ,
             W        	 => W        ,
	     berr	 => berr     ,
             SEL_ROMU_N  => E_ROMU_N ,
             SEL_RAMU_N  => E_RAMU_N ,
             SEL_ROMS_N  => E_ROMS_N ,
             SEL_RAMS_N  => E_RAMS_N ,
             SEL_TIMER_N => E_TIME_N ,
             SEL_ROMR_N  => E_ROMR_N ,
             SEL_ROME_N  => E_ROME_N ,
             VDD         => VDD      ,
             VSS         => VSS
             );

  timer : timer
  port map (
    CK      => CK,
    FRZ     => VSS,
    RESET_I => RESET,
    SEL     => DATA_ADR(4 downto 2),
    DATA    => DATA,
    RW      => RW,
    E_N     => E_TIME_N,
    RESET_O => RST,
    IRQ_N   => IRQ_N,
    VDD     => VDD,
    VSS     => VSS
    );

  ramu : sr64_32a
    port map (
             E_N => E_RAMU_N               ,
             W_N => RW                     ,
             DAT => DATA                   ,
             ADR => DATA_ADR ( 7 downto 2) ,
             VDD => VDD                    ,
             VSS => VSS
             );

  romu : romu
    port map (
             ADDRESS => DATA_ADR (7 downto 2) ,
             E_N     => E_ROMU_N              ,
             DATA    => DATA                  ,
             VDD     => VDD                   ,
             VSS     => VSS
             );

  rams : sr64_32a
    port map (
             E_N => E_RAMS_N               ,
             W_N => RW                     ,
             DAT => DATA                   ,
             ADR => DATA_ADR ( 7 downto 2) ,
             VDD => VDD                    ,
             VSS => VSS
             );

  roms : roms
    port map (
             ADDRESS => DATA_ADR (7 downto 2) ,
             E_N     => E_ROMS_N              ,
             DATA    => DATA                  ,
             VDD     => VDD                   ,
             VSS     => VSS
             );

 romr : romr
    port map (
             ADDRESS => DATA_ADR (7 downto 2) ,
             E_N     => E_ROMR_N              ,
             DATA    => DATA                  ,
             VDD     => VDD                   ,
             VSS     => VSS
             );
rome : rome
    port map (
             ADDRESS => DATA_ADR (7 downto 2) ,
             E_N     => E_ROME_N              ,
             DATA    => DATA                  ,
             VDD     => VDD                   ,
             VSS     => VSS
             );

end;