-- VHDL structural description generated from `mips_ctl` -- date : Fri Oct 31 12:01:00 1997 -- Entity Declaration ENTITY mips_ctl IS PORT ( ck : in BIT; -- ck frz : in BIT; -- frz reset : in BIT; -- reset scin : in BIT; -- scin scout : out BIT; -- scout test : in BIT; -- test berr : in BIT; -- berr w : out BIT_VECTOR (0 TO 1); -- w int : in BIT_VECTOR (5 DOWNTO 0); -- int rw_ctl : out BIT_VECTOR (15 DOWNTO 0); -- rw_ctl frz_ctl : out BIT_VECTOR (15 DOWNTO 0); -- frz_ctl wenable : out BIT_VECTOR (6 DOWNTO 0); -- wenable rf_aw : out BIT_VECTOR (4 DOWNTO 0); -- rf_aw rf_ar : out BIT_VECTOR (4 DOWNTO 0); -- rf_ar ctlopx : out BIT_VECTOR (8 DOWNTO 0); -- ctlopx ctlopy : out BIT_VECTOR (6 DOWNTO 0); -- ctlopy ctlalu : out BIT_VECTOR (5 DOWNTO 0); -- ctlalu ctlrw : out BIT_VECTOR (4 DOWNTO 1); -- ctlrw ctladr : out BIT; -- ctladr crsrout : out BIT_VECTOR (15 DOWNTO 0); -- crsrout alu_31_n : in BIT; -- alu_31_n alu_1_n : in BIT; -- alu_1_n alu_0_n : in BIT; -- alu_0_n adr_1_n : in BIT; -- adr_1_n adr_0_n : in BIT; -- adr_0_n crsrin : in BIT_VECTOR (15 DOWNTO 0); -- crsrin opx_sign : in BIT; -- opx_sign opy_sign : in BIT; -- opy_sign codop : in BIT_VECTOR (18 DOWNTO 0); -- codop rs : in BIT_VECTOR (4 DOWNTO 0); -- rs rd : in BIT_VECTOR (4 DOWNTO 0); -- rd rdrt : in BIT_VECTOR (4 DOWNTO 0); -- rdrt alu_test_n : out BIT; -- alu_test_n alu_c31_n : in BIT; -- alu_c31_n alu_c30_n : in BIT; -- alu_c30_n alu_nul : in BIT; -- alu_nul alu_sign : in BIT; -- alu_sign rw : out BIT; -- rw vdd : in BIT; -- vdd vss : in BIT -- vss ); END mips_ctl; -- Architecture Declaration ARCHITECTURE structural_view OF mips_ctl IS COMPONENT mips_seqo port ( ck : in BIT; -- ck frz : in BIT; -- frz rqs : in BIT; -- rqs reset : in BIT; -- reset resnul : in BIT; -- resnul alu_sign : in BIT; -- alu_sign ir_opcod : in BIT_VECTOR(18 DOWNTO 0); -- ir_opcod vdd : in BIT; -- vdd vss : in BIT; -- vss scin : in BIT; -- scin test : in BIT; -- test itrqs : in BIT; -- itrqs adrs : in BIT_VECTOR(1 DOWNTO 0); -- adrs exrqs : in BIT; -- exrqs ctlopx : out BIT_VECTOR(8 DOWNTO 0); -- ctlopx ctlopy : out BIT_VECTOR(6 DOWNTO 0); -- ctlopy ctlalu : out BIT_VECTOR(5 DOWNTO 0); -- ctlalu wenable : out BIT_VECTOR(10 DOWNTO 0); -- wenable ctlrw : out BIT_VECTOR(4 DOWNTO 0); -- ctlrw ctladr : out BIT; -- ctladr excp : out BIT_VECTOR(6 DOWNTO 0); -- excp scout : out BIT -- scout ); END COMPONENT; COMPONENT mips_sts port ( ck : in BIT; -- ck reset : in BIT; -- reset frz : in BIT; -- frz test : in BIT; -- test opx_sign : in BIT; -- opx_sign opy_sign : in BIT; -- opy_sign alu_sign : in BIT; -- alu_sign alu_nul : in BIT; -- alu_nul alu_c31 : in BIT; -- alu_c31 alu_c30 : in BIT; -- alu_c30 ctlalu : in BIT_VECTOR(5 DOWNTO 0); -- ctlalu rs : in BIT_VECTOR(4 DOWNTO 0); -- rs rd : in BIT_VECTOR(4 DOWNTO 0); -- rd rdrt : in BIT_VECTOR(4 DOWNTO 0); -- rdrt mxrs_rdrt : in BIT; -- mxrs_rdrt wenable_in : in BIT_VECTOR(10 DOWNTO 0); -- wenable_in ctlrw_in : in BIT_VECTOR(4 DOWNTO 0); -- ctlrw_in ctlrw_out : inout BIT_VECTOR(4 DOWNTO 1); -- ctlrw_out adr0 : in BIT; -- adr0 adr1 : in BIT; -- adr1 adr31 : in BIT; -- adr31 intrqs : in BIT_VECTOR(5 DOWNTO 0); -- intrqs intrqs_seq : out BIT; -- intrqs_seq berr_s : in BIT; -- berr_s scin : in BIT; -- scin alu_test : out BIT; -- alu_test redpnt : out BIT_VECTOR(4 DOWNTO 0); -- redpnt wrtpnt : out BIT_VECTOR(4 DOWNTO 0); -- wrtpnt wenable_out : out BIT_VECTOR(6 DOWNTO 0); -- wenable_out crsr_dpt : in BIT_VECTOR(15 DOWNTO 0); -- crsr_dpt crsr_out : out BIT_VECTOR(15 DOWNTO 0); -- crsr_out crsr_mx : in BIT; -- crsr_mx excp : in BIT_VECTOR(6 DOWNTO 0); -- excp rqs : out BIT; -- rqs exq : out BIT; -- exq rw : out BIT; -- rw rw_ctl : out BIT_VECTOR(15 DOWNTO 0); -- rw_ctl frz_ctl : out BIT_VECTOR(15 DOWNTO 0); -- frz_ctl w : out BIT_VECTOR(1 DOWNTO 0); -- w scout : out BIT; -- scout vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; SIGNAL ctlrw_int_0 : BIT; -- ctlrw_int 0 SIGNAL ctlrw_int_1 : BIT; -- ctlrw_int 1 SIGNAL ctlrw_int_2 : BIT; -- ctlrw_int 2 SIGNAL ctlrw_int_3 : BIT; -- ctlrw_int 3 SIGNAL ctlrw_int_4 : BIT; -- ctlrw_int 4 SIGNAL excp_0 : BIT; -- excp 0 SIGNAL excp_1 : BIT; -- excp 1 SIGNAL excp_2 : BIT; -- excp 2 SIGNAL excp_3 : BIT; -- excp 3 SIGNAL excp_4 : BIT; -- excp 4 SIGNAL excp_5 : BIT; -- excp 5 SIGNAL excp_6 : BIT; -- excp 6 SIGNAL exq : BIT; -- exq SIGNAL intrqs : BIT; -- intrqs SIGNAL rqs : BIT; -- rqs SIGNAL scan : BIT; -- scan SIGNAL wenable_int_0 : BIT; -- wenable_int 0 SIGNAL wenable_int_1 : BIT; -- wenable_int 1 SIGNAL wenable_int_2 : BIT; -- wenable_int 2 SIGNAL wenable_int_3 : BIT; -- wenable_int 3 SIGNAL wenable_int_4 : BIT; -- wenable_int 4 SIGNAL wenable_int_5 : BIT; -- wenable_int 5 SIGNAL wenable_int_6 : BIT; -- wenable_int 6 SIGNAL wenable_int_7 : BIT; -- wenable_int 7 SIGNAL wenable_int_8 : BIT; -- wenable_int 8 SIGNAL wenable_int_9 : BIT; -- wenable_int 9 SIGNAL wenable_int_10 : BIT; -- wenable_int 10 BEGIN seq : mips_seqo PORT MAP ( scout => scan, excp => excp_6& excp_5& excp_4& excp_3& excp_2& excp_1& excp_0, ctladr => ctladr, ctlrw => ctlrw_int_4& ctlrw_int_3& ctlrw_int_2& ctlrw_int_1& ctlrw_int_0, wenable => wenable_int_10& wenable_int_9& wenable_int_8& wenable_int_7& wenable_int_6& wenable_int_5& wenable_int_4& wenable_int_3& wenable_int_2& wenable_int_1& wenable_int_0, ctlalu => ctlalu(5)& ctlalu(4)& ctlalu(3)& ctlalu(2)& ctlalu(1)& ctlalu(0), ctlopy => ctlopy(6)& ctlopy(5)& ctlopy(4)& ctlopy(3)& ctlopy(2)& ctlopy(1)& ctlopy(0), ctlopx => ctlopx(8)& ctlopx(7)& ctlopx(6)& ctlopx(5)& ctlopx(4)& ctlopx(3)& ctlopx(2)& ctlopx(1)& ctlopx(0), exrqs => exq, adrs => adr_1_n& adr_0_n, itrqs => intrqs, test => test, scin => scin, vss => vss, vdd => vdd, ir_opcod => codop(18)& codop(17)& codop(16)& codop(15)& codop(14)& codop(13)& codop(12)& codop(11)& codop(10)& codop(9)& codop(8)& codop(7)& codop(6)& codop(5)& codop(4)& codop(3)& codop(2)& codop(1)& codop(0), alu_sign => alu_sign, resnul => alu_nul, reset => reset, rqs => rqs, frz => frz, ck => ck); sts : mips_sts PORT MAP ( vss => vss, vdd => vdd, scout => scout, w => w(1)& w(0), frz_ctl => frz_ctl(15)& frz_ctl(14)& frz_ctl(13)& frz_ctl(12)& frz_ctl(11)& frz_ctl(10)& frz_ctl(9)& frz_ctl(8)& frz_ctl(7)& frz_ctl(6)& frz_ctl(5)& frz_ctl(4)& frz_ctl(3)& frz_ctl(2)& frz_ctl(1)& frz_ctl(0), rw_ctl => rw_ctl(15)& rw_ctl(14)& rw_ctl(13)& rw_ctl(12)& rw_ctl(11)& rw_ctl(10)& rw_ctl(9)& rw_ctl(8)& rw_ctl(7)& rw_ctl(6)& rw_ctl(5)& rw_ctl(4)& rw_ctl(3)& rw_ctl(2)& rw_ctl(1)& rw_ctl(0), rw => rw, reset => reset, exq => exq, rqs => rqs, excp => excp_6& excp_5& excp_4& excp_3& excp_2& excp_1& excp_0, crsr_mx => ctlopx(0), crsr_out => crsrout(15)& crsrout(14)& crsrout(13)& crsrout(12)& crsrout(11)& crsrout(10)& crsrout(9)& crsrout(8)& crsrout(7)& crsrout(6)& crsrout(5)& crsrout(4)& crsrout(3)& crsrout(2)& crsrout(1)& crsrout(0), crsr_dpt => crsrin(15)& crsrin(14)& crsrin(13)& crsrin(12)& crsrin(11)& crsrin(10)& crsrin(9)& crsrin(8)& crsrin(7)& crsrin(6)& crsrin(5)& crsrin(4)& crsrin(3)& crsrin(2)& crsrin(1)& crsrin(0), wenable_out => wenable(6)& wenable(5)& wenable(4)& wenable(3)& wenable(2)& wenable(1)& wenable(0), wrtpnt => rf_aw(4)& rf_aw(3)& rf_aw(2)& rf_aw(1)& rf_aw(0), redpnt => rf_ar(4)& rf_ar(3)& rf_ar(2)& rf_ar(1)& rf_ar(0), alu_test => alu_test_n, scin => scan, berr_s => berr, intrqs_seq => intrqs, intrqs => int(5)& int(4)& int(3)& int(2)& int(1)& int(0), adr31 => alu_31_n, adr1 => alu_1_n, adr0 => alu_0_n, ctlrw_out => ctlrw(4)& ctlrw(3)& ctlrw(2)& ctlrw(1), ctlrw_in => ctlrw_int_4& ctlrw_int_3& ctlrw_int_2& ctlrw_int_1& ctlrw_int_0, wenable_in => wenable_int_10& wenable_int_9& wenable_int_8& wenable_int_7& wenable_int_6& wenable_int_5& wenable_int_4& wenable_int_3& wenable_int_2& wenable_int_1& wenable_int_0, mxrs_rdrt => ctlopx(0), rdrt => rdrt(4)& rdrt(3)& rdrt(2)& rdrt(1)& rdrt(0), rd => rd(4)& rd(3)& rd(2)& rd(1)& rd(0), rs => rs(4)& rs(3)& rs(2)& rs(1)& rs(0), ctlalu => ctlalu(5)& ctlalu(4)& ctlalu(3)& ctlalu(2)& ctlalu(1)& ctlalu(0), alu_c30 => alu_c30_n, alu_c31 => alu_c31_n, alu_nul => alu_nul, alu_sign => alu_sign, opy_sign => opy_sign, opx_sign => opx_sign, test => test, frz => frz, ck => ck); end structural_view;