DPGEN_RF1 3 ASIM/LIP6 DPGEN_RF1 DPGEN_RF1R0 Register File Macro-Generator #include <genlib.h> void GENLIB_MACRO DPGEN_RF1 char *modelname long flags long N void GENLIB_MACRO DPGEN_RF1R0 char *modelname long flags long N Generate a register file of ®Number; words of &N; bits whitout decoder named &modelname;. The &DPGEN-RF1R0; variant differs from the &DPGEN-RF1; in that the register of address zero is stuck to zero. You can write into it, it will not change the value. When read, it will always return zero. How it works : &datain0; and &datain1; : the two write busses. Only one is used to actually write the register word, it is selected by the &sel; signal. &sel; : when set to &zero; the &datain0; is used to write the register word, otherwise it will be &datain1;. &selr;, &selw; : this register file have no decoder, so &selr; have a bus width equal to ®Number;. One bit for each word. &ckok; : clock signal (input, 1 bit). &sel; : select the write bus (input, 1 bit). &selr; : the decoded read address (input, ®Number; bits). &selw; : the decoded write address (input, ®Number; bits). &datain0; : first write bus (input, &N; bits). &datain1; : second write bus (input, &N; bits). &dataout; : read bus (output, &N; bits). &vdd; : power. &vss; : ground. GENLIB_MACRO(DPGEN_RF1, "model_rf1x8_32" , F_BEHAV|F_PLACE , 32 /* Words size. */ , 8 /* Number of words. */ ); GENLIB_LOINS( "model_rf1x8_32" , "instance1_rf1_32" , "ckok" , "sel" , "selr[7:0]" , "selw[7:0]" , "datain0[31:0]" , "datain1[31:0]" , "dataout[31:0]" , "vdd", "vss", NULL ); &man-dpgen-see-also;