/*------------------------------------------------------------\ | | | This file is part of the Alliance CAD System Copyright | | (C) Laboratoire LIP6 - Département ASIM Universite P&M Curie| | | | Home page : http://www-asim.lip6.fr/alliance/ | | E-mail : mailto:alliance-users@asim.lip6.fr | | | | This progam is free software; you can redistribute it | | and/or modify it under the terms of the GNU General Public | | License as published by the Free Software Foundation; | | either version 2 of the License, or (at your option) any | | later version. | | | | Alliance VLSI CAD System is distributed in the hope that | | it will be useful, but WITHOUT ANY WARRANTY; | | without even the implied warranty of MERCHANTABILITY or | | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General | | Public License for more details. | | | | You should have received a copy of the GNU General Public | | License along with the GNU C Library; see the file COPYING. | | If not, write to the Free Software Foundation, Inc., | | 675 Mass Ave, Cambridge, MA 02139, USA. | | | \------------------------------------------------------------*/ /*------------------------------------------------------------\ | | | Tool : SYF | | | | File : syf_bdd.c | | | | Author : Jacomme Ludovic | | | | Date : 06.03.95 | | | \------------------------------------------------------------*/ /*------------------------------------------------------------\ | | | Include Files | | | \------------------------------------------------------------*/ # include "mut.h" # include "aut.h" # include "abl.h" # include "bdd.h" # include "fsm.h" # include "fvh.h" # include # include # include # include "syf_bdd.h" # include "syf_error.h" /*------------------------------------------------------------\ | | | Constants | | | \------------------------------------------------------------*/ /*------------------------------------------------------------\ | | | Types | | | \------------------------------------------------------------*/ /*------------------------------------------------------------\ | | | Variables | | | \------------------------------------------------------------*/ /*------------------------------------------------------------\ | | | Functions | | | \------------------------------------------------------------*/ /*------------------------------------------------------------\ | | | SyfFsmMakeBddCircuit | | | \------------------------------------------------------------*/ bddcircuit *SyfFsmMakeBddCircuit( BddSystem, FsmFigure ) bddsystem *BddSystem; fsmfig_list *FsmFigure; { fsmin_list *ScanIn; fsmout_list *ScanOut; bddcircuit *BddCircuit; BddCircuit = createbddcircuit( FsmFigure->NAME, FsmFigure->NUMBER_IN + FsmFigure->NUMBER_OUT, FsmFigure->NUMBER_STATE, BddSystem ); for ( ScanIn = FsmFigure->IN; ScanIn != (fsmin_list *)0; ScanIn = ScanIn->NEXT ) { addbddcircuitin( (bddcircuit *)0, ScanIn->NAME, (bddindex )0, BDD_IN_MODE_LAST ); } for ( ScanOut = FsmFigure->OUT; ScanOut != (fsmout_list *)0; ScanOut = ScanOut->NEXT ) { addbddcircuitin( (bddcircuit *)0, ScanOut->NAME, (bddindex )0, BDD_IN_MODE_LAST ); } FsmFigure->CIRCUIT = BddCircuit; makefsmbddnode( FsmFigure ); return( BddCircuit ); }