This is as.info, produced by makeinfo version 4.3 from as.texinfo. START-INFO-DIR-ENTRY * As: (as). The GNU assembler. * Gas: (as). The GNU assembler. END-INFO-DIR-ENTRY This file documents the GNU Assembler "as". Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".  File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960 `callj' ....... You can write `callj' to have the assembler or the linker determine the most appropriate form of subroutine call: `call', `bal', or `calls'. If the assembly source contains enough information--a `.leafproc' or `.sysproc' directive defining the operand--then `as' translates the `callj'; if not, it simply emits the `callj', leaving it for the linker to resolve.  File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960 Compare-and-Branch .................. The 960 architectures provide combined Compare-and-Branch instructions that permit you to store the branch target in the lower 13 bits of the instruction word itself. However, if you specify a branch target far enough away that its address won't fit in 13 bits, the assembler can either issue an error, or convert your Compare-and-Branch instruction into separate instructions to do the compare and the branch. Whether `as' gives an error or expands the instruction depends on two choices you can make: whether you use the `-no-relax' option, and whether you use a "Compare and Branch" instruction or a "Compare and Jump" instruction. The "Jump" instructions are _always_ expanded if necessary; the "Branch" instructions are expanded when necessary _unless_ you specify `-no-relax'--in which case `as' gives an error instead. These are the Compare-and-Branch instructions, their "Jump" variants, and the instruction pairs they may expand into: Compare and Branch Jump Expanded to ------ ------ ------------ bbc chkbit; bno bbs chkbit; bo cmpibe cmpije cmpi; be cmpibg cmpijg cmpi; bg cmpibge cmpijge cmpi; bge cmpibl cmpijl cmpi; bl cmpible cmpijle cmpi; ble cmpibno cmpijno cmpi; bno cmpibne cmpijne cmpi; bne cmpibo cmpijo cmpi; bo cmpobe cmpoje cmpo; be cmpobg cmpojg cmpo; bg cmpobge cmpojge cmpo; bge cmpobl cmpojl cmpo; bl cmpoble cmpojle cmpo; ble cmpobne cmpojne cmpo; bne  File: as.info, Node: IP2K-Dependent, Next: M32R-Dependent, Prev: i960-Dependent, Up: Machine Dependencies IP2K Dependent Features ======================= * Menu: * IP2K-Opts:: IP2K Options  File: as.info, Node: IP2K-Opts, Up: IP2K-Dependent IP2K Options ------------ The Ubicom IP2K version of `as' has a few machine dependent options: `-mip2022ext' `as' can assemble the extended IP2022 instructions, but it will only do so if this is specifically allowed via this command line option. `-mip2022' This option restores the assembler's default behaviour of not permitting the extended IP2022 instructions to be assembled.  File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies M32R Dependent Features ======================= * Menu: * M32R-Opts:: M32R Options * M32R-Warnings:: M32R Warnings  File: as.info, Node: M32R-Opts, Next: M32R-Warnings, Up: M32R-Dependent M32R Options ------------ The Renease M32R version of `as' has a few machine dependent options: `-m32rx' `as' can assemble code for several different members of the Renesas M32R family. Normally the default is to assemble code for the M32R microprocessor. This option may be used to change the default to the M32RX microprocessor, which adds some more instructions to the basic M32R instruction set, and some additional parameters to some of the original instructions. `-m32r' This option can be used to restore the assembler's default behaviour of assembling for the M32R microprocessor. This can be useful if the default has been changed by a previous command line option. `-warn-explicit-parallel-conflicts' Instructs `as' to produce warning messages when questionable parallel instructions are encountered. This option is enabled by default, but `gcc' disables it when it invokes `as' directly. Questionable instructions are those whoes behaviour would be different if they were executed sequentially. For example the code fragment `mv r1, r2 || mv r3, r1' produces a different result from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 and r3. `-Wp' This is a shorter synonym for the _-warn-explicit-parallel-conflicts_ option. `-no-warn-explicit-parallel-conflicts' Instructs `as' not to produce warning messages when questionable parallel instructions are encountered. `-Wnp' This is a shorter synonym for the _-no-warn-explicit-parallel-conflicts_ option.  File: as.info, Node: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent M32R Warnings ------------- There are several warning and error messages that can be produced by `as' which are specific to the M32R: `output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the left hand instruction is used as an input register in the right hand instruction. For example in this code fragment `mv r1, r2 || neg r3, r1' register r1 is the destination of the move instruction and the input to the neg instruction. `output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the right hand instruction is used as an input register in the left hand instruction. For example in this code fragment `mv r1, r2 || neg r2, r3' register r2 is the destination of the neg instruction and the input to the move instruction. `instruction `...' is for the M32RX only' This message is produced when the assembler encounters an instruction which is only supported by the M32Rx processor, and the `-m32rx' command line flag has not been specified to allow assembly of such instructions. `unknown instruction `...'' This message is produced when the assembler encounters an instruction which it doe snot recognise. `only the NOP instruction can be issued in parallel on the m32r' This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the `-m32rx' command line flag has not been specified. Only the M32Rx processor is able to execute two instructions in parallel. `instruction `...' cannot be executed in parallel.' This message is produced when the assembler encounters a parallel instruction which is made up of one or two instructions which cannot be executed in parallel. `Instructions share the same execution pipeline' This message is produced when the assembler encounters a parallel instruction whoes components both use the same execution pipeline. `Instructions write to the same destination register.' This message is produced when the assembler encounters a parallel instruction where both components attempt to modify the same register. For example these code fragments will produce this message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2, @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx r3, r4' (Both write to the condition bit)  File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies M680x0 Dependent Features ========================= * Menu: * M68K-Opts:: M680x0 Options * M68K-Syntax:: Syntax * M68K-Moto-Syntax:: Motorola Syntax * M68K-Float:: Floating Point * M68K-Directives:: 680x0 Machine Directives * M68K-opcodes:: Opcodes  File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent M680x0 Options -------------- The Motorola 680x0 version of `as' has a few machine dependent options: `-l' You can use the `-l' option to shorten the size of references to undefined symbols. If you do not use the `-l' option, references to undefined symbols are wide enough for a full `long' (32 bits). (Since `as' cannot know where these symbols end up, `as' can only allocate space for the linker to fill in later. Since `as' does not know how far away these symbols are, it allocates as much space as it can.) If you use this option, the references are only one word wide (16 bits). This may be useful if you want the object file to be as small as possible, and you know that the relevant symbols are always less than 17 bits away. `--register-prefix-optional' For some configurations, especially those where the compiler normally does not prepend an underscore to the names of user variables, the assembler requires a `%' before any use of a register name. This is intended to let the assembler distinguish between C variables and functions named `a0' through `a7', and so on. The `%' is always accepted, but is not required for certain configurations, notably `sun3'. The `--register-prefix-optional' option may be used to permit omitting the `%' even for configurations for which it is normally required. If this is done, it will generally be impossible to refer to C variables and functions with the same names as register names. `--bitwise-or' Normally the character `|' is treated as a comment character, which means that it can not be used in expressions. The `--bitwise-or' option turns `|' into a normal character. In this mode, you must either use C style comments, or start comments with a `#' character at the beginning of a line. `--base-size-default-16 --base-size-default-32' If you use an addressing mode with a base register without specifying the size, `as' will normally use the full 32 bit value. For example, the addressing mode `%a0@(%d0)' is equivalent to `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to tell `as' to default to using the 16 bit value. In this case, `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the `--base-size-default-32' option to restore the default behaviour. `--disp-size-default-16 --disp-size-default-32' If you use an addressing mode with a displacement, and the value of the displacement is not known, `as' will normally assume that the value is 32 bits. For example, if the symbol `disp' has not been defined, `as' will assemble the addressing mode `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use the `--disp-size-default-16' option to tell `as' to instead assume that the displacement is 16 bits. In this case, `as' will assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You may use the `--disp-size-default-32' option to restore the default behaviour. `--pcrel' Always keep branches PC-relative. In the M680x0 architecture all branches are defined as PC-relative. However, on some processors they are limited to word displacements maximum. When `as' needs a long branch that is not available, it normally emits an absolute jump instead. This option disables this substitution. When this option is given and no long branches are available, only word branches will be emitted. An error message will be generated if a word branch cannot reach its target. This option has no effect on 68020 and other processors that have long branches. *note Branch Improvement: M68K-Branch.. `-m68000' `as' can assemble code for several different members of the Motorola 680x0 family. The default depends upon how `as' was configured when it was built; normally, the default is to assemble code for the 68020 microprocessor. The following options may be used to change the default. These options control which instructions and addressing modes are permitted. The members of the 680x0 family are very similar. For detailed information about the differences, see the Motorola manuals. `-m68000' `-m68ec000' `-m68hc000' `-m68hc001' `-m68008' `-m68302' `-m68306' `-m68307' `-m68322' `-m68356' Assemble for the 68000. `-m68008', `-m68302', and so on are synonyms for `-m68000', since the chips are the same from the point of view of the assembler. `-m68010' Assemble for the 68010. `-m68020' `-m68ec020' Assemble for the 68020. This is normally the default. `-m68030' `-m68ec030' Assemble for the 68030. `-m68040' `-m68ec040' Assemble for the 68040. `-m68060' `-m68ec060' Assemble for the 68060. `-mcpu32' `-m68330' `-m68331' `-m68332' `-m68333' `-m68334' `-m68336' `-m68340' `-m68341' `-m68349' `-m68360' Assemble for the CPU32 family of chips. `-m5200' Assemble for the ColdFire family of chips. `-m68881' `-m68882' Assemble 68881 floating point instructions. This is the default for the 68020, 68030, and the CPU32. The 68040 and 68060 always support floating point instructions. `-mno-68881' Do not assemble 68881 floating point instructions. This is the default for 68000 and the 68010. The 68040 and 68060 always support floating point instructions, even if this option is used. `-m68851' Assemble 68851 MMU instructions. This is the default for the 68020, 68030, and 68060. The 68040 accepts a somewhat different set of MMU instructions; `-m68851' and `-m68040' should not be used together. `-mno-68851' Do not assemble 68851 MMU instructions. This is the default for the 68000, 68010, and the CPU32. The 68040 accepts a somewhat different set of MMU instructions.  File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent Syntax ------ This syntax for the Motorola 680x0 was developed at MIT. The 680x0 version of `as' uses instructions names and syntax compatible with the Sun assembler. Intervening periods are ignored; for example, `movl' is equivalent to `mov.l'. In the following table APC stands for any of the address registers (`%a0' through `%a7'), the program counter (`%pc'), the zero-address relative to the program counter (`%zpc'), a suppressed address register (`%za0' through `%za7'), or it may be omitted entirely. The use of SIZE means one of `w' or `l', and it may be omitted, along with the leading colon, unless a scale is also specified. The use of SCALE means one of `1', `2', `4', or `8', and it may always be omitted along with the leading colon. The following addressing modes are understood: "Immediate" `#NUMBER' "Data Register" `%d0' through `%d7' "Address Register" `%a0' through `%a7' `%a7' is also known as `%sp', i.e. the Stack Pointer. `%a6' is also known as `%fp', the Frame Pointer. "Address Register Indirect" `%a0@' through `%a7@' "Address Register Postincrement" `%a0@+' through `%a7@+' "Address Register Predecrement" `%a0@-' through `%a7@-' "Indirect Plus Offset" `APC@(NUMBER)' "Index" `APC@(NUMBER,REGISTER:SIZE:SCALE)' The NUMBER may be omitted. "Postindex" `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' The ONUMBER or the REGISTER, but not both, may be omitted. "Preindex" `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' The NUMBER may be omitted. Omitting the REGISTER produces the Postindex addressing mode. "Absolute" `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'.  File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent Motorola Syntax --------------- The standard Motorola syntax for this chip differs from the syntax already discussed (*note Syntax: M68K-Syntax.). `as' can accept Motorola syntax for operands, even if MIT syntax is used for other operands in the same instruction. The two kinds of syntax are fully compatible. In the following table APC stands for any of the address registers (`%a0' through `%a7'), the program counter (`%pc'), the zero-address relative to the program counter (`%zpc'), or a suppressed address register (`%za0' through `%za7'). The use of SIZE means one of `w' or `l', and it may always be omitted along with the leading dot. The use of SCALE means one of `1', `2', `4', or `8', and it may always be omitted along with the leading asterisk. The following additional addressing modes are understood: "Address Register Indirect" `(%a0)' through `(%a7)' `%a7' is also known as `%sp', i.e. the Stack Pointer. `%a6' is also known as `%fp', the Frame Pointer. "Address Register Postincrement" `(%a0)+' through `(%a7)+' "Address Register Predecrement" `-(%a0)' through `-(%a7)' "Indirect Plus Offset" `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'. The NUMBER may also appear within the parentheses, as in `(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted (with an address register, omitting the NUMBER produces Address Register Indirect mode). "Index" `NUMBER(APC,REGISTER.SIZE*SCALE)' The NUMBER may be omitted, or it may appear within the parentheses. The APC may be omitted. The REGISTER and the APC may appear in either order. If both APC and REGISTER are address registers, and the SIZE and SCALE are omitted, then the first register is taken as the base register, and the second as the index register. "Postindex" `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' The ONUMBER, or the REGISTER, or both, may be omitted. Either the NUMBER or the APC may be omitted, but not both. "Preindex" `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' The NUMBER, or the APC, or the REGISTER, or any two of them, may be omitted. The ONUMBER may be omitted. The REGISTER and the APC may appear in either order. If both APC and REGISTER are address registers, and the SIZE and SCALE are omitted, then the first register is taken as the base register, and the second as the index register.  File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent Floating Point -------------- Packed decimal (P) format floating literals are not supported. Feel free to add the code! The floating point formats generated by directives are these. `.float' `Single' precision floating point constants. `.double' `Double' precision floating point constants. `.extend' `.ldouble' `Extended' precision (`long double') floating point constants.  File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent 680x0 Machine Directives ------------------------ In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives. `.data1' This directive is identical to a `.data 1' directive. `.data2' This directive is identical to a `.data 2' directive. `.even' This directive is a special case of the `.align' directive; it aligns the output to an even byte boundary. `.skip' This directive is identical to a `.space' directive.  File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent Opcodes ------- * Menu: * M68K-Branch:: Branch Improvement * M68K-Chars:: Special Characters  File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes Branch Improvement .................. Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by substituting `j' for `b' at the start of a Motorola mnemonic. The following table summarizes the pseudo-operations. A `*' flags cases that are more fully described after the table: Displacement +------------------------------------------------------------ | 68020 68000/10, not PC-relative OK Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** +------------------------------------------------------------ jbsr |bsrs bsrw bsrl jsr jra |bras braw bral jmp * jXX |bXXs bXXw bXXl bNXs;jmp * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp fjXX | N/A fbXXw fbXXl N/A XX: condition NX: negative of condition XX `*'--see full description below `**'--this expansion mode is disallowed by `--pcrel' `jbsr' `jra' These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target. This instruction will be a byte or word branch is that is sufficient. Otherwise, a long branch will be emitted if available. If no long branches are available and the `--pcrel' option is not given, an absolute long jump will be emitted instead. If no long branches are available, the `--pcrel' option is given, and a word branch cannot reach the target, an error message is generated. In addition to standard branch operands, `as' allows these pseudo-operations to have all operands that are allowed for jsr and jmp, substituting these instructions if the operand given is not valid for a branch instruction. `jXX' Here, `jXX' stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is: jhi jls jcc jcs jne jeq jvc jvs jpl jmi jge jlt jgt jle Usually, each of these pseudo-operations expands to a single branch instruction. However, if a word branch is not sufficient, no long branches are available, and the `--pcrel' option is not given, `as' issues a longer code fragment in terms of NX, the opposite condition to XX. For example, under these conditions: jXX foo gives bNXs oof jmp foo oof: `dbXX' The full family of pseudo-operations covered here is dbhi dbls dbcc dbcs dbne dbeq dbvc dbvs dbpl dbmi dbge dblt dbgt dble dbf dbra dbt Motorola `dbXX' instructions allow word displacements only. When a word displacement is sufficient, each of these pseudo-operations expands to the corresponding Motorola instruction. When a word displacement is not sufficient and long branches are available, when the source reads `dbXX foo', `as' emits dbXX oo1 bras oo2 oo1:bral foo oo2: If, however, long branches are not available and the `--pcrel' option is not given, `as' emits dbXX oo1 bras oo2 oo1:jmp foo oo2: `fjXX' This family includes fjne fjeq fjge fjlt fjgt fjle fjf fjt fjgl fjgle fjnge fjngl fjngle fjngt fjnle fjnlt fjoge fjogl fjogt fjole fjolt fjor fjseq fjsf fjsne fjst fjueq fjuge fjugt fjule fjult fjun Each of these pseudo-operations always expands to a single Motorola coprocessor branch instruction, word or long. All Motorola coprocessor branch instructions allow both word and long displacements.  File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes Special Characters .................. The immediate character is `#' for Sun compatibility. The line-comment character is `|' (unless the `--bitwise-or' option is used). If a `#' appears at the beginning of a line, it is treated as a comment unless it looks like `# line file', in which case it is treated normally.  File: as.info, Node: M68HC11-Dependent, Next: M88K-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies M68HC11 and M68HC12 Dependent Features ====================================== * Menu: * M68HC11-Opts:: M68HC11 and M68HC12 Options * M68HC11-Syntax:: Syntax * M68HC11-Modifiers:: Symbolic Operand Modifiers * M68HC11-Directives:: Assembler Directives * M68HC11-Float:: Floating Point * M68HC11-opcodes:: Opcodes  File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent M68HC11 and M68HC12 Options --------------------------- The Motorola 68HC11 and 68HC12 version of `as' have a few machine dependent options. `-m68hc11' This option switches the assembler in the M68HC11 mode. In this mode, the assembler only accepts 68HC11 operands and mnemonics. It produces code for the 68HC11. `-m68hc12' This option switches the assembler in the M68HC12 mode. In this mode, the assembler also accepts 68HC12 operands and mnemonics. It produces code for the 68HC12. A few 68HC11 instructions are replaced by some 68HC12 instructions as recommended by Motorola specifications. `-m68hcs12' This option switches the assembler in the M68HCS12 mode. This mode is similar to `-m68hc12' but specifies to assemble for the 68HCS12 series. The only difference is on the assembling of the `movb' and `movw' instruction when a PC-relative operand is used. `-mshort' This option controls the ABI and indicates to use a 16-bit integer ABI. It has no effect on the assembled instructions. This is the default. `-mlong' This option controls the ABI and indicates to use a 32-bit integer ABI. `-mshort-double' This option controls the ABI and indicates to use a 32-bit float ABI. This is the default. `-mlong-double' This option controls the ABI and indicates to use a 64-bit float ABI. `--strict-direct-mode' You can use the `--strict-direct-mode' option to disable the automatic translation of direct page mode addressing into extended mode when the instruction does not support direct mode. For example, the `clr' instruction does not support direct page mode addressing. When it is used with the direct page mode, `as' will ignore it and generate an absolute addressing. This option prevents `as' from doing this, and the wrong usage of the direct page mode will raise an error. `--short-branchs' The `--short-branchs' option turns off the translation of relative branches into absolute branches when the branch offset is out of range. By default `as' transforms the relative branch (`bsr', `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', `bls', `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch when the offset is out of the -128 .. 127 range. In that case, the `bsr' instruction is translated into a `jsr', the `bra' instruction is translated into a `jmp' and the conditional branchs instructions are inverted and followed by a `jmp'. This option disables these translations and `as' will generate an error if a relative branch is out of range. This option does not affect the optimization associated to the `jbra', `jbsr' and `jbXX' pseudo opcodes. `--force-long-branchs' The `--force-long-branchs' option forces the translation of relative branches into absolute branches. This option does not affect the optimization associated to the `jbra', `jbsr' and `jbXX' pseudo opcodes. `--print-insn-syntax' You can use the `--print-insn-syntax' option to obtain the syntax description of the instruction when an error is detected. `--print-opcodes' The `--print-opcodes' option prints the list of all the instructions with their syntax. The first item of each line represents the instruction name and the rest of the line indicates the possible operands for that instruction. The list is printed in alphabetical order. Once the list is printed `as' exits. `--generate-example' The `--generate-example' option is similar to `--print-opcodes' but it generates an example for each instruction instead.  File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent Syntax ------ In the M68HC11 syntax, the instruction name comes first and it may be followed by one or several operands (up to three). Operands are separated by comma (`,'). In the normal mode, `as' will complain if too many operands are specified for a given instruction. In the MRI mode (turned on with `-M' option), it will treat them as comments. Example: inx lda #23 bset 2,x #4 brclr *bot #8 foo The following addressing modes are understood for 68HC11 and 68HC12: "Immediate" `#NUMBER' "Address Register" `NUMBER,X', `NUMBER,Y' The NUMBER may be omitted in which case 0 is assumed. "Direct Addressing mode" `*SYMBOL', or `*DIGITS' "Absolute" `SYMBOL', or `DIGITS' The M68HC12 has other more complex addressing modes. All of them are supported and they are represented below: "Constant Offset Indexed Addressing Mode" `NUMBER,REG' The NUMBER may be omitted in which case 0 is assumed. The register can be either `X', `Y', `SP' or `PC'. The assembler will use the smaller post-byte definition according to the constant value (5-bit constant offset, 9-bit constant offset or 16-bit constant offset). If the constant is not known by the assembler it will use the 16-bit constant offset post-byte and the value will be resolved at link time. "Offset Indexed Indirect" `[NUMBER,REG]' The register can be either `X', `Y', `SP' or `PC'. "Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+' The number must be in the range `-8'..`+8' and must not be 0. The register can be either `X', `Y', `SP' or `PC'. "Accumulator Offset" `ACC,REG' The accumulator register can be either `A', `B' or `D'. The register can be either `X', `Y', `SP' or `PC'. "Accumulator D offset indexed-indirect" `[D,REG]' The register can be either `X', `Y', `SP' or `PC'. For example: ldab 1024,sp ldd [10,x] orab 3,+x stab -2,y- ldx a,pc sty [d,sp]  File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent Symbolic Operand Modifiers -------------------------- The assembler supports several modifiers when using symbol addresses in 68HC11 and 68HC12 instruction operands. The general syntax is the following: %modifier(symbol) `%addr' This modifier indicates to the assembler and linker to use the 16-bit physical address corresponding to the symbol. This is intended to be used on memory window systems to map a symbol in the memory bank window. If the symbol is in a memory expansion part, the physical address corresponds to the symbol address within the memory bank window. If the symbol is not in a memory expansion part, this is the symbol address (using or not using the %addr modifier has no effect in that case). `%page' This modifier indicates to use the memory page number corresponding to the symbol. If the symbol is in a memory expansion part, its page number is computed by the linker as a number used to map the page containing the symbol in the memory bank window. If the symbol is not in a memory expansion part, the page number is 0. `%hi' This modifier indicates to use the 8-bit high part of the physical address of the symbol. `%lo' This modifier indicates to use the 8-bit low part of the physical address of the symbol. For example a 68HC12 call to a function `foo_example' stored in memory expansion part could be written as follows: call %addr(foo_example),%page(foo_example) and this is equivalent to call foo_example And for 68HC11 it could be written as follows: ldab #%page(foo_example) stab _page_switch jsr %addr(foo_example)  File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent Assembler Directives -------------------- The 68HC11 and 68HC12 version of `as' have the following specific assembler directives: `.relax' The relax directive is used by the `GNU Compiler' to emit a specific relocation to mark a group of instructions for linker relaxation. The sequence of instructions within the group must be known to the linker so that relaxation can be performed. `.mode [mshort|mlong|mshort-double|mlong-double]' This directive specifies the ABI. It overrides the `-mshort', `-mlong', `-mshort-double' and `-mlong-double' options. `.far SYMBOL' This directive marks the symbol as a `far' symbol meaning that it uses a `call/rtc' calling convention as opposed to `jsr/rts'. During a final link, the linker will identify references to the `far' symbol and will verify the proper calling convention. `.interrupt SYMBOL' This directive marks the symbol as an interrupt entry point. This information is then used by the debugger to correctly unwind the frame across interrupts. `.xrefb SYMBOL' This directive is defined for compatibility with the `Specification for Motorola 8 and 16-Bit Assembly Language Input Standard' and is ignored.  File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent Floating Point -------------- Packed decimal (P) format floating literals are not supported. Feel free to add the code! The floating point formats generated by directives are these. `.float' `Single' precision floating point constants. `.double' `Double' precision floating point constants. `.extend' `.ldouble' `Extended' precision (`long double') floating point constants.  File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent Opcodes ------- * Menu: * M68HC11-Branch:: Branch Improvement  File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes Branch Improvement .................. Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by prepending `j' to the start of Motorola mnemonic. These pseudo opcodes are not affected by the `--short-branchs' or `--force-long-branchs' options. The following table summarizes the pseudo-operations. Displacement Width +-------------------------------------------------------------+ | Options | | --short-branchs --force-long-branchs | +--------------------------+----------------------------------+ Op |BYTE WORD | BYTE WORD | +--------------------------+----------------------------------+ bsr | bsr | jsr | bra | bra | jmp | jbsr | bsr jsr | bsr jsr | jbra | bra jmp | bra jmp | bXX | bXX | bNX +3; jmp | jbXX | bXX bNX +3; | bXX bNX +3; jmp | | jmp | | +--------------------------+----------------------------------+ XX: condition NX: negative of condition XX `jbsr' `jbra' These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target. `jbXX' Here, `jbXX' stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is: jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo jbcs jbne jblt jble jbls jbvc jbmi For the cases of non-PC relative displacements and long displacements, `as' issues a longer code fragment in terms of NX, the opposite condition to XX. For example, for the non-PC relative case: jbXX foo gives bNXs oof jmp foo oof:  File: as.info, Node: M88K-Dependent, Next: MIPS-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies Motorola M88K Dependent Features ================================ * Menu: * M88K Directives:: M88K Machine Directives  File: as.info, Node: M88K Directives, Up: M88K-Dependent M88K Machine Directives ----------------------- The M88K version of the assembler supports the following machine directives: `.align' This directive aligns the section program counter on the next 4-byte boundary. `.dfloat EXPR' This assembles a double precision (64-bit) floating point constant. `.ffloat EXPR' This assembles a single precision (32-bit) floating point constant. `.half EXPR' This directive assembles a half-word (16-bit) constant. `.word EXPR' This assembles a word (32-bit) constant. `.string "STR"' This directive behaves like the standard `.ascii' directive for copying STR into the object file. The string is not terminated with a null byte. `.set SYMBOL, VALUE' This directive creates a symbol named SYMBOL which is an alias for another symbol (possibly not yet defined). This should not be confused with the mnemonic `set', which is a legitimate M88K instruction. `.def SYMBOL, VALUE' This directive is synonymous with `.set' and is presumably provided for compatibility with other M88K assemblers. `.bss SYMBOL, LENGTH, ALIGN' Reserve LENGTH bytes in the bss section for a local SYMBOL, aligned to the power of two specified by ALIGN. LENGTH and ALIGN must be positive absolute expressions. This directive differs from `.lcomm' only in that it permits you to specify an alignment. *Note `.lcomm': Lcomm.  File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: M88K-Dependent, Up: Machine Dependencies MIPS Dependent Features ======================= GNU `as' for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For information about the MIPS instruction set, see `MIPS RISC Architecture', by Kane and Heindrich (Prentice-Hall). For an overview of MIPS assembly conventions, see "Appendix D: Assembly Language Programming" in the same work. * Menu: * MIPS Opts:: Assembler options * MIPS Object:: ECOFF object code * MIPS Stabs:: Directives for debugging information * MIPS ISA:: Directives to override the ISA level * MIPS autoextend:: Directives for extending MIPS 16 bit instructions * MIPS insn:: Directive to mark data as an instruction * MIPS option stack:: Directives to save and restore options * MIPS ASE instruction generation overrides:: Directives to control generation of MIPS ASE instructions  File: as.info, Node: MIPS Opts, Next: MIPS Object, Up: MIPS-Dependent Assembler options ----------------- The MIPS configurations of GNU `as' support these special options: `-G NUM' This option sets the largest size of an object that can be referenced implicitly with the `gp' register. It is only accepted for targets that use ECOFF format. The default value is 8. `-EB' `-EL' Any MIPS configuration of `as' can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other). Use `-EB' to select big-endian output, and `-EL' for little-endian. `-mips1' `-mips2' `-mips3' `-mips4' `-mips5' `-mips32' `-mips32r2' `-mips64' Generate code for a particular MIPS Instruction Set Architecture level. `-mips1' corresponds to the R2000 and R3000 processors, `-mips2' to the R6000 processor, `-mips3' to the R4000 processor, and `-mips4' to the R8000 and R10000 processors. `-mips5', `-mips32', `-mips32r2', and `-mips64' correspond to generic MIPS V, MIPS32, MIPS32 RELEASE 2, and MIPS64 ISA processors, respectively. You can also switch instruction sets during the assembly; see *Note Directives to override the ISA level: MIPS ISA. `-mgp32' `-mfp32' Some macros have different expansions for 32-bit and 64-bit registers. The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. `-mgp32' controls the size of general-purpose registers and `-mfp32' controls the size of floating-point registers. On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap. Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers. `-mgp64' Assume that 64-bit general purpose registers are available. This is provided in the interests of symmetry with -gp32. `-mips16' `-no-mips16' Generate code for the MIPS 16 processor. This is equivalent to putting `.set mips16' at the start of the assembly file. `-no-mips16' turns off this option. `-mips3d' `-no-mips3d' Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. `-no-mips3d' turns off this option. `-mdmx' `-no-mdmx' Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. `-no-mdmx' turns off this option. `-mfix7000' `-mno-fix7000' Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. `-mfix-vr4122-bugs' `-no-mfix-vr4122-bugs' Insert `nop' instructions to avoid errors in certain versions of the vr4122 core. This option is intended to be used on GCC-generated code: it is not designed to catch errors in hand-written assembler code. `-m4010' `-no-m4010' Generate code for the LSI R4010 chip. This tells the assembler to accept the R4010 specific instructions (`addciu', `ffc', etc.), and to not schedule `nop' instructions around accesses to the `HI' and `LO' registers. `-no-m4010' turns off this option. `-m4650' `-no-m4650' Generate code for the MIPS R4650 chip. This tells the assembler to accept the `mad' and `madu' instruction, and to not schedule `nop' instructions around accesses to the `HI' and `LO' registers. `-no-m4650' turns off this option. `-m3900' `-no-m3900' `-m4100' `-no-m4100' For each option `-mNNNN', generate code for the MIPS RNNNN chip. This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards. `-march=CPU' Generate code for a particular MIPS cpu. It is exactly equivalent to `-mCPU', except that there are more value of CPU understood. Valid CPU value are: 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, 10000, 12000, mips32-4k, sb1 `-mtune=CPU' Schedule and tune for a particular MIPS cpu. Valid CPU values are identical to `-march=CPU'. `-mabi=ABI' Record which ABI the source code uses. The recognized arguments are: `32', `n32', `o64', `64' and `eabi'. `-nocpp' This option is ignored. It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing. With GNU `as', there is no need for `-nocpp', because the GNU assembler itself never runs the C preprocessor. `--construct-floats' `--no-construct-floats' The `--no-construct-floats' option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. This feature is useful if the processor support the FR bit in its status register, and this bit is known (by the programmer) to be set. This bit prevents the aliasing of the double width register by the single width registers. By default `--construct-floats' is selected, allowing construction of these floating point constants. `--trap' `--no-break' `as' automatically macro expands certain division and multiplication instructions to check for overflow and division by zero. This option causes `as' to generate code to take a trap exception rather than a break exception when an error is detected. The trap instructions are only supported at Instruction Set Architecture level 2 and higher. `--break' `--no-trap' Generate code to take a break exception rather than a trap exception when an error is detected. This is the default. `-n' When this option is used, `as' will issue a warning every time it generates a nop instruction from a macro.  File: as.info, Node: MIPS Object, Next: MIPS Stabs, Prev: MIPS Opts, Up: MIPS-Dependent MIPS ECOFF object code ---------------------- Assembling for a MIPS ECOFF target supports some additional sections besides the usual `.text', `.data' and `.bss'. The additional sections are `.rdata', used for read-only data, `.sdata', used for small data, and `.sbss', used for small common objects. When assembling for ECOFF, the assembler uses the `$gp' (`$28') register to form the address of a "small object". Any object in the `.sdata' or `.sbss' sections is considered "small" in this sense. For external objects, or for objects in the `.bss' section, you can use the `gcc' `-G' option to control the size of objects addressed via `$gp'; the default value is 8, meaning that a reference to any object eight bytes or smaller uses `$gp'. Passing `-G 0' to `as' prevents it from using the `$gp' register on the basis of object size (but the assembler uses `$gp' for objects in `.sdata' or `sbss' in any case). The size of an object in the `.bss' section is set by the `.comm' or `.lcomm' directive that defines it. The size of an external object may be set with the `.extern' directive. For example, `.extern sym,4' declares that the object at `sym' is 4 bytes in length, whie leaving `sym' otherwise undefined. Using small ECOFF objects requires linker support, and assumes that the `$gp' register is correctly initialized (normally done automatically by the startup code). MIPS ECOFF assembly code must not modify the `$gp' register.  File: as.info, Node: MIPS Stabs, Next: MIPS ISA, Prev: MIPS Object, Up: MIPS-Dependent Directives for debugging information ------------------------------------ MIPS ECOFF `as' supports several directives used for generating debugging information which are not support by traditional MIPS assemblers. These are `.def', `.endef', `.dim', `.file', `.scl', `.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'. The debugging information generated by the three `.stab' directives can only be read by GDB, not by traditional MIPS debuggers (this enhancement is required to fully support C++ debugging). These directives are primarily used by compilers, not assembly language programmers!