list p=18f452 ; list directive to define processor include ; processor specific variable definitions include ; Grab some useful macros .command macro x .direct "C", x endm ;---------------------------------------------------------------------- ;---------------------------------------------------------------------- GPR_DATA UDATA temp RES 1 temp1 RES 1 temp2 RES 1 failures RES 1 a2dIntFlag RES 1 ;LSB is set when an A2D interrupt occurs GLOBAL done GLOBAL a2dIntFlag ;------------------------------------------------------------------------ STARTUP CODE 0 bra Start ;------------------------------------------------------------------------ ; ; Interrupt Vector ; ;------------------------------------------------------------------------ INT_VECTOR CODE 0x008 ; interrupt vector location check_TMR0_interrupt: btfsc PIR1,ADIF ;If A2D int flag is not set btfsc PIE1,ADIE ;Or the interrupt is not enabled goto a2dint .assert "\"FAIL 18F452 unexpected interrupt\"" nop RETFIE 1 ; Then leave ;; An A/D interrupt has occurred a2dint: bsf a2dIntFlag,0 ;Set a flag to indicate we got the int. bcf ADCON0,ADIF ;Clear the a/d interrupt ExitInterrupt: RETFIE 1 ;---------------------------------------------------------------------- ; ******************* MAIN CODE START LOCATION ****************** ;---------------------------------------------------------------------- MAIN CODE .sim "module library libgpsim_modules" ; Use a pullup resistor as a voltage source .sim "module load pullup V1" .sim "V1.resistance = 100.0" .sim "module load pullup V2" .sim "V2.resistance = 100.0" ; V3 and na1 required for A/D to see voltage bug ? ; RRR 5/06 .sim "module load pullup V3" .sim "V3.resistance = 10e6" .sim "node na0" .sim "attach na0 V1.pin porta0" .sim "node na1" .sim "attach na1 V3.pin porta1" .sim "node na3" .sim "attach na3 V2.pin porta3" Start: ; RA0 is an Analog Input. ; RA1 - RA5 are all configured as outputs. ; ; Use VDD and VSS for Voltage references. ; ; PCFG = 1110 == AN0 is the only analog input ; ADCS = 110 == FOSC/64 ; ADFM = 0 == 6 LSB of ADRESL are 0. ; MOVLW 1<