/*      Oak Techologies OTI-067/077/087 mode definitions

 *      12 September 1994 Christopher M. Wiles (a0017097@wsuaix.csc.wsu.edu)
 *      The below mode definitions work just fine on my '87 board.  As I
 *      do not have either a '67 or a '77 to play with, I cannot guarantee
 *      that any or all of these modes will work with cards based on those
 *      chips.  Therefore, use at your own risk (and let me know if they work).
 *
 *      NB: If any of these modes are displaced horizontally, change the fifth
 *      byte (in units of 8) of the CRTC section in the definition in 
 *      question.  Increment the value to move the screen left, decrement to
 *      move the screen right.
 */

#define PATCH1			/* g640x480x256_regs */
#define PATCH2			/* g800x600x16_regs */
#define PATCH3			/* still g800x600x16_regs */
#define PATCH4			/* g800x600x256_regs */

static const unsigned char g640x480x256_regs[79] =
{
	/* CRTC */
  0x63, 0x4F, 0x50, 0x86, 0x58, 0x81, 0x06, 0x3E, 0x00, 0x40, 0x00, 0x00,
  0x00, 0x00, 0x00, 0x00, 0xE8, 0x8b, 0xDF, 0x28, 0x00, 0xE4, 0x01, 0xC3,
	/* ATC */
  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
    0x0c, 0x0d, 0x0e, 0x0f, 0x01, 0x00, 0x0f, 0x00, 0x00,
	/* Graphics */
    0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff,
	/* Sequencer */
#ifdef PATCH1
/* SEQ reg 1 bit 3 broke my 067. It may now break the 87s, for all I know! */
    0x03, 0x01, 0x0f, 0x00, 0x0e,
#else
    0x03, 0x09, 0x0f, 0x00, 0x0e,
#endif
	/* Misc. output */
    0xE3,
	/* Extended registers */
    0xC0, 0x8F, 0x80, 0x00, 0x01, 0x00, 0x00, 0xFF,
	/* 087 native registers */
    0x0f, 0x00, 0x00, 0x00, 0x0f, 0x04, 0x04, 0x00,
    0x00, 0x00, 0x00

};

static const unsigned char g800x600x16_regs[79] =
{
	/* CRTC */
  0x7f, 0x63, 0x64, 0x82, 0x6c, 0x1f, 0x72, 0xf0, 0x00, 0x60, 0x00, 0x00,
  0x00, 0x00, 0x00, 0x00, 0x58, 0x8c, 0x57, 0x32, 0x0f, 0x58, 0x6e, 0xe3,
	/* ATC */
#ifdef PATCH2
/* There is something wrong with my palette in this mode. Setting the
   palette-regs to the first entries in the 256-color table seems
   to lessen the problem (but not remove it). */
  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
    0x0c, 0x0d, 0x0e, 0x0f, 0x01, 0x00, 0x0f, 0x00, 0x00,
#else
  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, 0x38, 0x39, 0x3a, 0x3b,
    0x3c, 0x3d, 0x3e, 0x3f, 0x01, 0x00, 0x0f, 0x00, 0x00,
#endif
	/* Graphics */
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff,
	/* Sequencer */
    0x03, 0x01, 0x0f, 0x00, 0x06,
	/* Misc. output */
    0xeb,
	/* Extended registers */
#ifdef PATCH3
/* Setting all bits in 3de reg E broke my 67. Only bit 7 is documented
   anyway, so this should also work on 87's. I hope. */
    0x00, 0x28, 0x80, 0x00, 0xff, 0x00, 0x00, 0xff,
#else
    0x00, 0x28, 0xff, 0x00, 0xff, 0x00, 0x00, 0xff,
#endif
	/* 087 Native registers */
    0x06, 0x00, 0x40, 0x00, 0x0f, 0x03, 0x00, 0x08,
    0x00, 0x00, 0x00

};

static const unsigned char g800x600x256_regs[79] =
{
	/* CRTC */
  0x7f, 0x63, 0x64, 0x82, 0x6c, 0x1f, 0x72, 0xf0, 0x00, 0x60, 0x00, 0x00,
  0x00, 0x00, 0x00, 0x00, 0x58, 0x8c, 0x57, 0x32, 0x0f, 0x58, 0x6e, 0xe3,
	/* ATC */
  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
    0x0c, 0x0d, 0x0e, 0x0f, 0x01, 0x00, 0x0f, 0x00, 0x00,
	/* Graphics */
    0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff,
	/* Sequencer */
    0x03, 0x01, 0x0f, 0x00, 0x0e,
	/* Misc. output */
    0xeb,
	/* Extended registers */
/* Setting all bits in 3de reg e broke my 67. Only bit 7 is documented
   anyway, so this should also work on 87's. I hope. */
#ifdef PATCH4
    0x00, 0x2e, 0x80, 0x00, 0xff, 0x00, 0x40, 0xff,
#else
    0x00, 0x2e, 0xff, 0x00, 0xff, 0x00, 0x40, 0xff,
#endif
	/* 087 native registers */
    0x06, 0x00, 0x40, 0x00, 0x0f, 0x06, 0x04, 0x08,
    0x00, 0x00, 0x00

};

static const unsigned char g1024x768x256_regs[79] =
{
	/* CRTC */
  0xa3, 0x7f, 0x80, 0x86, 0x89, 0x9a, 0x24, 0xfd, 0x00, 0x60, 0x00, 0x00,
  0x00, 0x00, 0x00, 0x00, 0x02, 0x88, 0xff, 0x40, 0x0f, 0x02, 0x20, 0xe3,
	/* ATC */
  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
    0x0c, 0x0d, 0x0e, 0x0f, 0x01, 0x00, 0x0f, 0x00, 0x00,
	/* Graphics */
    0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff,
	/* Sequencer */
    0x03, 0x01, 0x0f, 0x00, 0x0e,
	/* Misc. output */
    0x2b,
	/* Extended registers */
    0x00, 0x0d, 0xff, 0x00, 0xff, 0x00, 0x4f, 0xff,
	/* 087 native registers */
    0x0b, 0x00, 0x4f, 0x00, 0x0f, 0x05, 0x04, 0x04,
    0x00, 0x00, 0x00

};

static const unsigned char g640x480x32K_regs[79] =
{
	/* CRTC */
  0xcb, 0x9f, 0xa1, 0x8d, 0xad, 0x0f, 0x0b, 0x3e, 0x00, 0x40, 0x00, 0x00,
  0x00, 0x00, 0x00, 0x00, 0xe8, 0x8b, 0xdf, 0x50, 0x00, 0xe4, 0x01, 0xc3,
	/* ATC */
  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
    0x0c, 0x0d, 0x0e, 0x0f, 0x01, 0x00, 0x0f, 0x00, 0x00,
	/* Graphics */
    0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff,
	/* Sequencer */
    0x03, 0x01, 0x0f, 0x00, 0x0e,
	/* Misc. output */
    0xe3,
	/* Extended registers */
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	/* 087 native registers */
    0x0f, 0x00, 0x00, 0x00, 0x0f, 0x08, 0x04, 0x08,
    0x00, 0x00, 0xa0
};

static const unsigned char g800x600x32K_regs[79] =
{
	/* CRTC */
  0xff, 0xc7, 0xc9, 0x81, 0xd9, 0x04, 0x72, 0xf0, 0x00, 0x60, 0x00, 0x00,
  0x00, 0x00, 0x00, 0x00, 0x58, 0x8c, 0x57, 0x64, 0x0f, 0x58, 0x6e, 0xe3,
	/* ATC */
  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
    0x0c, 0x0d, 0x0e, 0x0f, 0x01, 0x00, 0x0f, 0x00, 0x00,
	/* Graphics */
    0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff,
	/* Sequencer */
    0x03, 0x01, 0x0f, 0x00, 0x0e,
	/* Misc. output */
    0xeb,
	/* Extended registers */
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	/* 087 native registers */
    0x0a, 0x00, 0x00, 0x00, 0x0f, 0x0a, 0x04, 0x08,
    0x00, 0x00, 0xa0

};

static const unsigned char g1280x1024x16_regs[79] =
{
	/* CRTC */
  0xc3, 0x9f, 0xa0, 0x86, 0xa2, 0x17, 0x2e, 0xb2, 0x00, 0x60, 0x00, 0x00,
  0x00, 0x00, 0x00, 0x00, 0x0d, 0x9c, 0xff, 0x50, 0x0f, 0x04, 0x29, 0xe3,
	/* ATC */
  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, 0x38, 0x39, 0x3a, 0x3b,
    0x3c, 0x3d, 0x3e, 0x3f, 0x01, 0x00, 0x0f, 0x00, 0x00,
	/* Graphics */
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff,
	/* Sequencer */
    0x03, 0x01, 0x0f, 0x00, 0x06,
	/* Misc. output */
    0x2b,
	/* Extended registers */
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	/* 087 native registers */
    0x0a, 0x80, 0x4f, 0x00, 0x0f, 0x05, 0x00, 0x08,
    0x00, 0x00, 0x00

};

/* HighRes 16 color modes based on 256 color modes */
#define g1024x768x16_regs g1024x768x256_regs