static const x86_info_operand insn_operands[] = {
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
    {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_XMM0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
    {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
    {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
    {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
    {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_ST0, OPS_80, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Reg, OPS_80, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
    {OPT_Reg, OPS_80, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
    {OPT_ST0, OPS_80, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_8, 1, 1, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_16, 1, 1, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_32, 1, 1, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_64, 1, 1, OPTM_None, OPA_EA, OPAP_None},
    {OPT_MemOffs, OPS_8, 1, 1, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_16, 1, 1, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_32, 1, 1, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_64, 1, 1, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Imm, OPS_64, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_MemOffs, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemOffs, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
    {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
    {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
    {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
    {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Imm, OPS_64, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Imm, OPS_64, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm32Avail},
    {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_CR4, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_CR4, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemrAX, OPS_Any, 0, 0, OPTM_None, OPA_AdSizeEA, OPAP_None},
    {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
    {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_Any, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_Any, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
    {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
    {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
    {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
    {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
    {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
    {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
    {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
    {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
    {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
    {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
    {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
    {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
    {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
    {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
    {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
    {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
    {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
    {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_Mem, OPS_Any, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_A16},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
    {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Mem, OPS_80, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Mem, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Mem, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
    {OPT_SS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_SS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_DS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_DS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_DS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_ES, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_ES, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_ES, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_FS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_FS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_FS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_GS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_GS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_GS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_MemEAX, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_ImmNotSegOff, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
    {OPT_ImmNotSegOff, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
    {OPT_ImmNotSegOff, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
    {OPT_Imm, OPS_16, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
    {OPT_Imm, OPS_32, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
    {OPT_Imm, OPS_Any, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
    {OPT_RM, OPS_16, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
    {OPT_RM, OPS_32, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
    {OPT_RM, OPS_64, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
    {OPT_Mem, OPS_Any, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
    {OPT_Mem, OPS_16, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
    {OPT_Mem, OPS_32, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
    {OPT_Mem, OPS_64, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
    {OPT_Mem, OPS_Any, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
    {OPT_Imm, OPS_16, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
    {OPT_Imm, OPS_32, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
    {OPT_Imm, OPS_Any, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
    {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
    {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
    {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
    {OPT_Reg, OPS_80, 0, 0, OPTM_To, OPA_Op1Add, OPAP_None},
    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
    {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
    {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_SImm, OPAP_None},
    {OPT_Imm, OPS_BITS, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
    {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
    {OPT_CS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_CS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
    {OPT_CS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}
};

static const x86_insn_info empty_insn[] = {
    { 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
};

static const x86_insn_info not64_insn[] = {
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
};

static const x86_insn_info onebyte_insn[] = {
    { 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, MOD_DOpS64R}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 0, 0 }
};

static const x86_insn_info onebyte_prefix_insn[] = {
    { 0, 0, 0, 0, {MOD_PreAdd, MOD_Op0Add, 0}, 0, 0, 0x00, 0, 1, {0x00, 0, 0}, 0, 0, 0 }
};

static const x86_insn_info twobyte_insn[] = {
    { SUF_L|SUF_Q, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 0, 0 }
};

static const x86_insn_info threebyte_insn[] = {
    { 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, MOD_Op2Add}, 0, 0, 0, 0, 3, {0x00, 0x00, 0x00}, 0, 0, 0 }
};

static const x86_insn_info onebytemem_insn[] = {
    { SUF_L|SUF_Q|SUF_S, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 402 }
};

static const x86_insn_info twobytemem_insn[] = {
    { SUF_L|SUF_Q|SUF_S|SUF_W, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 0, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 402 }
};

static const x86_insn_info mov_insn[] = {
    { SUF_B, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 253 },
    { SUF_W, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 255 },
    { SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 257 },
    { SUF_B, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 259 },
    { SUF_W, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 261 },
    { SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 263 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 229 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 231 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 233 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 235 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 237 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 239 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 241 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 243 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x88, 0xA2, 0}, 0, 2, 265 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 267 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 269 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 271 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x88, 0, 0}, 0, 2, 211 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x89, 0, 0}, 0, 2, 165 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x89, 0, 0}, 0, 2, 171 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x89, 0, 0}, 0, 2, 177 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8A, 0xA0, 0}, 0, 2, 273 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 275 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 277 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 279 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8A, 0, 0}, 0, 2, 213 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 84 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 87 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 90 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 281 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 283 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 285 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 287 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 289 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 284 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 286 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xB0, 0, 0}, 0, 2, 291 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 293 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 295 },
    { GAS_ILLEGAL, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 297 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2, 299 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 301 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 303 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 305 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 307 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 309 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 311 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 313 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 315 },
    { SUF_L, CPU_586, CPU_Not64, CPU_Priv, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 317 },
    { SUF_L, CPU_386, CPU_Not64, CPU_Priv, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 319 },
    { SUF_Q, CPU_64, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 321 },
    { SUF_L, CPU_586, CPU_Not64, CPU_Priv, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 323 },
    { SUF_L, CPU_386, CPU_Not64, CPU_Priv, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 318 },
    { SUF_Q, CPU_64, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 325 },
    { SUF_L, CPU_386, CPU_Not64, CPU_Priv, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 327 },
    { SUF_Q, CPU_64, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 329 },
    { SUF_L, CPU_386, CPU_Not64, CPU_Priv, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 328 },
    { SUF_Q, CPU_64, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 331 },
    { GAS_ONLY|SUF_Q, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 159 },
    { GAS_ONLY|SUF_Q, CPU_64, CPU_MMX, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 191 },
    { GAS_ONLY|SUF_Q, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 219 },
    { GAS_ONLY|SUF_Q, CPU_64, CPU_MMX, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 193 },
    { GAS_ONLY|SUF_Q, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 0 },
    { GAS_ONLY|SUF_Q, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 221 },
    { GAS_ONLY|SUF_Q, CPU_64, CPU_SSE2, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 162 },
    { GAS_ONLY|SUF_Q, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 223 },
    { GAS_ONLY|SUF_Q, CPU_64, CPU_SSE2, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 147 }
};

static const x86_insn_info movabs_insn[] = {
    { SUF_B, CPU_64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 229 },
    { SUF_W, CPU_64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 231 },
    { SUF_L, CPU_64, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 233 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 235 },
    { SUF_B, CPU_64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 237 },
    { SUF_W, CPU_64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 239 },
    { SUF_L, CPU_64, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 241 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 243 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 245 }
};

static const x86_insn_info movszx_insn[] = {
    { SUF_B, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 429 },
    { SUF_B, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 379 },
    { SUF_B, CPU_64, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 383 },
    { SUF_W, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 381 },
    { SUF_W, CPU_64, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 431 }
};

static const x86_insn_info movsxd_insn[] = {
    { SUF_L, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, 463 }
};

static const x86_insn_info push_insn[] = {
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x50, 0, 0}, 0, 1, 293 },
    { SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x50, 0, 0}, 0, 1, 295 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x50, 0, 0}, 0, 1, 245 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 183 },
    { SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 185 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 187 },
    { GAS_ILLEGAL, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x6A, 0, 0}, 0, 1, 86 },
    { GAS_ONLY, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x6A, 0, 0}, 0, 1, 510 },
    { GAS_ONLY|SUF_W, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 406 },
    { GAS_ONLY|SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 408 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 98 },
    { GAS_ILLEGAL, CPU_186, CPU_Not64, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 511 },
    { GAS_ILLEGAL, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x68, 0, 0}, 0, 1, 304 },
    { GAS_ILLEGAL, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x68, 0, 0}, 0, 1, 306 },
    { GAS_ILLEGAL, CPU_64, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0x68, 0, 0}, 0, 1, 512 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 513 },
    { SUF_W, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 514 },
    { SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 515 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 469 },
    { SUF_W, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 470 },
    { SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 471 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 472 },
    { SUF_W, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 473 },
    { SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 474 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 475 },
    { SUF_W, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 476 },
    { SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 477 },
    { 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 478 },
    { SUF_W, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 479 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 480 },
    { 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 481 },
    { SUF_W, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 482 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 483 }
};

static const x86_insn_info pop_insn[] = {
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x58, 0, 0}, 0, 1, 293 },
    { SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x58, 0, 0}, 0, 1, 295 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x58, 0, 0}, 0, 1, 245 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 183 },
    { SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 185 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 187 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 469 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 470 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 471 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 472 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 473 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 474 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 475 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 476 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 477 },
    { 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 478 },
    { 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 479 },
    { 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 480 },
    { 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 481 },
    { 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 482 },
    { 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 483 }
};

static const x86_insn_info xchg_insn[] = {
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 211 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 213 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 359 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 361 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 165 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 84 },
    { SUF_L, CPU_64, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 363 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 365 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 367 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 171 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 87 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 369 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 244 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 371 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 177 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 90 }
};

static const x86_insn_info in_insn[] = {
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 2, 346 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 348 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 447 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 2, 352 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xED, 0, 0}, 0, 2, 354 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xED, 0, 0}, 0, 2, 350 },
    { GAS_ONLY|SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 1, 3 },
    { GAS_ONLY|SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
    { GAS_ONLY|SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
    { GAS_ONLY|SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 1, 351 },
    { GAS_ONLY|SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xED, 0, 0}, 0, 1, 351 },
    { GAS_ONLY|SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xED, 0, 0}, 0, 1, 351 }
};

static const x86_insn_info out_insn[] = {
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 2, 345 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 347 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 349 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 2, 351 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 353 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 355 },
    { GAS_ONLY|SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 1, 3 },
    { GAS_ONLY|SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
    { GAS_ONLY|SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
    { GAS_ONLY|SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 1, 351 },
    { GAS_ONLY|SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 351 },
    { GAS_ONLY|SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 351 }
};

static const x86_insn_info lea_insn[] = {
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 373 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 247 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 375 }
};

static const x86_insn_info ldes_insn[] = {
    { SUF_W, CPU_Not64, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 401 },
    { SUF_L, CPU_386, CPU_Not64, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 403 }
};

static const x86_insn_info lfgss_insn[] = {
    { SUF_W, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 401 },
    { SUF_L, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 403 }
};

static const x86_insn_info arith_insn[] = {
    { SUF_B, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2, 346 },
    { SUF_W, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 16, 0, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 405 },
    { SUF_L, CPU_386, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 32, 0, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 407 },
    { SUF_Q, CPU_64, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 64, 0, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 409 },
    { SUF_B, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 309 },
    { SUF_B, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 301 },
    { SUF_W, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0x83, 0, 0}, 0, 2, 411 },
    { GAS_ILLEGAL, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 413 },
    { SUF_W, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 415 },
    { SUF_L, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0x83, 0, 0}, 0, 2, 417 },
    { GAS_ILLEGAL, CPU_386, CPU_Not64, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 419 },
    { SUF_L, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 421 },
    { SUF_Q, CPU_64, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 1, {0x83, 0, 0}, 0, 2, 423 },
    { SUF_Q, CPU_64, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 425 },
    { SUF_B, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 211 },
    { SUF_W, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x01, 0, 0}, 0, 2, 165 },
    { SUF_L, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x01, 0, 0}, 0, 2, 171 },
    { SUF_Q, CPU_64, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 0, 1, {0x01, 0, 0}, 0, 2, 177 },
    { SUF_B, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x02, 0, 0}, 0, 2, 213 },
    { SUF_W, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x03, 0, 0}, 0, 2, 84 },
    { SUF_L, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x03, 0, 0}, 0, 2, 87 },
    { SUF_Q, CPU_64, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 0, 1, {0x03, 0, 0}, 0, 2, 90 }
};

static const x86_insn_info incdec_insn[] = {
    { SUF_B, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0xFE, 0, 0}, 0, 1, 309 },
    { SUF_W, CPU_Not64, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 293 },
    { SUF_W, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 183 },
    { SUF_L, CPU_386, CPU_Not64, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 295 },
    { SUF_L, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 185 },
    { SUF_Q, CPU_64, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 187 }
};

static const x86_insn_info f6_insn[] = {
    { SUF_B, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 309 },
    { SUF_W, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 183 },
    { SUF_L, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 185 },
    { SUF_Q, CPU_64, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 187 }
};

static const x86_insn_info div_insn[] = {
    { SUF_B, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 309 },
    { SUF_W, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 183 },
    { SUF_L, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 185 },
    { SUF_Q, CPU_64, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 187 },
    { SUF_B, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 335 },
    { SUF_W, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 337 },
    { SUF_L, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 339 },
    { SUF_Q, CPU_64, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 341 }
};

static const x86_insn_info test_insn[] = {
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA8, 0, 0}, 0, 2, 346 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 451 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 453 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 455 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 309 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 301 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 311 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 303 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 313 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 305 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 315 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 307 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 211 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 165 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 171 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 177 },
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 213 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 84 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 87 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 90 }
};

static const x86_insn_info aadm_insn[] = {
    { 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 2, {0xD4, 0x0A, 0}, 0, 0, 0 },
    { 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0xD4, 0, 0}, 0, 1, 3 }
};

static const x86_insn_info imul_insn[] = {
    { SUF_B, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 5, 1, 309 },
    { SUF_W, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 183 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 185 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 187 },
    { SUF_W, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 84 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 87 },
    { SUF_Q, CPU_386, CPU_64, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 90 },
    { SUF_W, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 84 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 87 },
    { SUF_Q, CPU_186, CPU_64, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 90 },
    { SUF_W, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 195 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 197 },
    { SUF_Q, CPU_186, CPU_64, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 199 },
    { SUF_W, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 93 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 96 },
    { SUF_Q, CPU_186, CPU_64, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 99 },
    { SUF_W, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 201 },
    { SUF_L, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 203 },
    { SUF_Q, CPU_186, CPU_64, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 205 }
};

static const x86_insn_info shift_insn[] = {
    { SUF_B, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD2, 0, 0}, 0, 2, 385 },
    { SUF_B, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 2, 387 },
    { SUF_B, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xC0, 0, 0}, 0, 2, 309 },
    { SUF_W, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 389 },
    { SUF_W, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 391 },
    { SUF_W, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 183 },
    { SUF_L, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 393 },
    { SUF_L, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 395 },
    { SUF_L, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 185 },
    { SUF_Q, CPU_64, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 397 },
    { SUF_Q, CPU_64, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 399 },
    { SUF_Q, CPU_186, CPU_64, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 187 },
    { GAS_ONLY|SUF_B, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 1, 309 },
    { GAS_ONLY|SUF_W, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 183 },
    { GAS_ONLY|SUF_L, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 185 },
    { GAS_ONLY|SUF_Q, CPU_64, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 187 }
};

static const x86_insn_info shlrd_insn[] = {
    { SUF_W, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 165 },
    { SUF_W, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 168 },
    { SUF_L, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 171 },
    { SUF_L, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 174 },
    { SUF_Q, CPU_386, CPU_64, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 177 },
    { SUF_Q, CPU_386, CPU_64, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 180 },
    { GAS_ONLY|SUF_W, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 165 },
    { GAS_ONLY|SUF_L, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 171 },
    { GAS_ONLY|SUF_Q, CPU_386, CPU_64, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 177 }
};

static const x86_insn_info call_insn[] = {
    { 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 485 },
    { 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 486 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 487 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 487 },
    { 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 488 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 489 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 489 },
    { 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 490 },
    { 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 183 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 185 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 187 },
    { 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 402 },
    { 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 491 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 492 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 493 },
    { 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 494 },
    { 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 495 },
    { 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 496 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 497 },
    { 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 498 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 499 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 500 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 501 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 502 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 503 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 504 }
};

static const x86_insn_info jmp_insn[] = {
    { 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 485 },
    { 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 486 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 487 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 487 },
    { 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xEB, 0, 0}, 0, 1, 439 },
    { 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 488 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 489 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 489 },
    { 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 490 },
    { 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 183 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 185 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 187 },
    { 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 402 },
    { 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 491 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 492 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 493 },
    { 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 494 },
    { 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 495 },
    { 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 496 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 497 },
    { 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 498 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 499 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 500 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 501 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 502 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 503 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 504 }
};

static const x86_insn_info retnf_insn[] = {
    { 0, CPU_Not64, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
    { 0, CPU_Not64, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 294 },
    { 0, CPU_64, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
    { 0, CPU_64, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 294 },
    { SUF_L|SUF_Q|SUF_W, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
    { SUF_L|SUF_Q|SUF_W, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 294 }
};

static const x86_insn_info enter_insn[] = {
    { GAS_NO_REV|SUF_L, CPU_186, CPU_Not64, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 461 },
    { GAS_NO_REV|SUF_Q, CPU_186, CPU_64, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 461 },
    { GAS_ONLY|GAS_NO_REV|SUF_W, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 461 }
};

static const x86_insn_info jcc_insn[] = {
    { 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 433 },
    { 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 508 },
    { 0, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 509 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 509 },
    { 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0x70, 0, 0}, 0, 1, 439 },
    { 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 16, 64, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 488 },
    { 0, CPU_386, CPU_Not64, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 489 },
    { 0, CPU_64, 0, 0, {MOD_Op1Add, 0, 0}, 64, 64, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 489 },
    { 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 0, 64, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 490 }
};

static const x86_insn_info jcxz_insn[] = {
    { 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 433 },
    { 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 64, 0, 0, 1, {0xE3, 0, 0}, 0, 1, 439 }
};

static const x86_insn_info loop_insn[] = {
    { 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 433 },
    { 0, CPU_Not64, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 2, 433 },
    { 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 0, {0, 0, 0}, 0, 2, 435 },
    { 0, CPU_64, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 0, {0, 0, 0}, 0, 2, 437 },
    { 0, CPU_Not64, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0xE0, 0, 0}, 0, 1, 439 },
    { 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0xE0, 0, 0}, 0, 2, 439 },
    { 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0xE0, 0, 0}, 0, 2, 441 },
    { 0, CPU_64, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0xE0, 0, 0}, 0, 2, 443 }
};

static const x86_insn_info setcc_insn[] = {
    { SUF_B, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x90, 0}, 2, 1, 211 }
};

static const x86_insn_info cmpsd_insn[] = {
    { GAS_ILLEGAL, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA7, 0, 0}, 0, 0, 0 },
    { 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0xC2, 0}, 0, 3, 29 }
};

static const x86_insn_info movsd_insn[] = {
    { GAS_ILLEGAL, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA5, 0, 0}, 0, 0, 0 },
    { 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x10, 0}, 0, 2, 0 },
    { 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x10, 0}, 0, 2, 25 },
    { 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x11, 0}, 0, 2, 46 }
};

static const x86_insn_info bittest_insn[] = {
    { SUF_W, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 165 },
    { SUF_L, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 171 },
    { SUF_Q, CPU_386, CPU_64, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 177 },
    { SUF_W, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 183 },
    { SUF_L, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 185 },
    { SUF_Q, CPU_386, CPU_64, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 187 }
};

static const x86_insn_info bsfr_insn[] = {
    { SUF_W, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 84 },
    { SUF_L, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 87 },
    { SUF_Q, CPU_386, CPU_64, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 90 }
};

static const x86_insn_info int_insn[] = {
    { 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xCD, 0, 0}, 0, 1, 3 }
};

static const x86_insn_info bound_insn[] = {
    { SUF_W, CPU_186, CPU_Not64, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x62, 0, 0}, 0, 2, 373 },
    { SUF_L, CPU_386, CPU_Not64, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x62, 0, 0}, 0, 2, 247 }
};

static const x86_insn_info arpl_insn[] = {
    { SUF_W, CPU_286, CPU_Not64, CPU_Prot, {0, 0, 0}, 0, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, 165 }
};

static const x86_insn_info str_insn[] = {
    { SUF_W, CPU_286, CPU_Prot, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 283 },
    { SUF_L, CPU_386, CPU_Prot, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 103 },
    { SUF_Q, CPU_286, CPU_64, CPU_Prot, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 106 },
    { SUF_L|SUF_W, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 85 }
};

static const x86_insn_info prot286_insn[] = {
    { SUF_W, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 85 }
};

static const x86_insn_info sldtmsw_insn[] = {
    { SUF_W, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 109 },
    { SUF_L, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 66 },
    { SUF_Q, CPU_286, CPU_64, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 26 },
    { SUF_W, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 283 },
    { SUF_L, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 103 },
    { SUF_Q, CPU_286, CPU_64, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 106 }
};

static const x86_insn_info fld_insn[] = {
    { SUF_S, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 467 },
    { SUF_L, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 468 },
    { 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 5, 1, 465 },
    { 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC0, 0}, 0, 1, 216 }
};

static const x86_insn_info fstp_insn[] = {
    { SUF_S, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 3, 1, 467 },
    { SUF_L, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 3, 1, 468 },
    { 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 7, 1, 465 },
    { 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xDD, 0xD8, 0}, 0, 1, 216 }
};

static const x86_insn_info fldstpt_insn[] = {
    { 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 465 }
};

static const x86_insn_info fildstp_insn[] = {
    { SUF_S, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 466 },
    { SUF_L, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 467 },
    { SUF_Q, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op0Add, MOD_SpAdd}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 468 }
};

static const x86_insn_info fbldstp_insn[] = {
    { 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 378 }
};

static const x86_insn_info fst_insn[] = {
    { SUF_S, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 2, 1, 467 },
    { SUF_L, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 2, 1, 468 },
    { 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xDD, 0xD0, 0}, 0, 1, 216 }
};

static const x86_insn_info fxch_insn[] = {
    { 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 1, 216 },
    { 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 215 },
    { 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 217 },
    { 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC9, 0}, 0, 0, 0 }
};

static const x86_insn_info fcom_insn[] = {
    { SUF_S, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 467 },
    { SUF_L, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 468 },
    { 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 216 },
    { GAS_ONLY, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xD8, 0x01, 0}, 0, 0, 0 },
    { GAS_ILLEGAL, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 215 }
};

static const x86_insn_info fcom2_insn[] = {
    { 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 216 },
    { 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 215 }
};

static const x86_insn_info farith_insn[] = {
    { SUF_S, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 467 },
    { SUF_L, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 468 },
    { 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 216 },
    { 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 215 },
    { 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 1, 505 },
    { GAS_ILLEGAL, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 217 },
    { GAS_ONLY, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 217 }
};

static const x86_insn_info farithp_insn[] = {
    { 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDE, 0x01, 0}, 0, 0, 0 },
    { 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 1, 216 },
    { 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 2, 217 }
};

static const x86_insn_info fiarith_insn[] = {
    { SUF_S, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 0, 1, {0x04, 0, 0}, 0, 1, 466 },
    { SUF_L, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 467 }
};

static const x86_insn_info fldnstcw_insn[] = {
    { SUF_W, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 109 }
};

static const x86_insn_info fstcw_insn[] = {
    { SUF_W, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x9B, 0xD9, 0}, 7, 1, 109 }
};

static const x86_insn_info fnstsw_insn[] = {
    { SUF_W, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 7, 1, 109 },
    { SUF_W, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xDF, 0xE0, 0}, 0, 1, 231 }
};

static const x86_insn_info fstsw_insn[] = {
    { SUF_W, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x9B, 0xDD, 0}, 7, 1, 109 },
    { SUF_W, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x9B, 0xDF, 0xE0}, 0, 1, 231 }
};

static const x86_insn_info ffree_insn[] = {
    { 0, CPU_FPU, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 2, {0x00, 0xC0, 0}, 0, 1, 216 }
};

static const x86_insn_info bswap_insn[] = {
    { SUF_L, CPU_486, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 506 },
    { SUF_Q, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 507 }
};

static const x86_insn_info cmpxchgxadd_insn[] = {
    { SUF_B, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 211 },
    { SUF_W, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 165 },
    { SUF_L, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 171 },
    { SUF_Q, CPU_486, CPU_64, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 177 }
};

static const x86_insn_info cmpxchg8b_insn[] = {
    { SUF_Q, CPU_586, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 26 }
};

static const x86_insn_info cmovcc_insn[] = {
    { SUF_W, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 84 },
    { SUF_L, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 87 },
    { SUF_Q, CPU_64, CPU_686, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 90 }
};

static const x86_insn_info fcmovcc_insn[] = {
    { 0, CPU_686, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 215 }
};

static const x86_insn_info movnti_insn[] = {
    { SUF_L, CPU_P4, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 225 },
    { SUF_Q, CPU_64, CPU_P4, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 227 }
};

static const x86_insn_info clflush_insn[] = {
    { 0, CPU_P3, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 7, 1, 124 }
};

static const x86_insn_info movd_insn[] = {
    { 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 189 },
    { 0, CPU_64, CPU_MMX, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 191 },
    { 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 190 },
    { 0, CPU_64, CPU_MMX, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 193 },
    { 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 120 },
    { 0, CPU_64, CPU_SSE2, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 162 },
    { 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 150 },
    { 0, CPU_64, CPU_SSE2, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 147 }
};

static const x86_insn_info movq_insn[] = {
    { GAS_ILLEGAL, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 159 },
    { GAS_ILLEGAL, CPU_64, CPU_MMX, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 191 },
    { GAS_ILLEGAL, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 219 },
    { GAS_ILLEGAL, CPU_64, CPU_MMX, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 193 },
    { GAS_ILLEGAL, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 0 },
    { GAS_ILLEGAL, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 221 },
    { GAS_ILLEGAL, CPU_64, CPU_SSE2, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 162 },
    { GAS_ILLEGAL, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 223 },
    { GAS_ILLEGAL, CPU_64, CPU_SSE2, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 147 }
};

static const x86_insn_info mmxsse2_insn[] = {
    { 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 159 },
    { 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0}, 0, 2, 5 }
};

static const x86_insn_info pshift_insn[] = {
    { 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 159 },
    { 0, CPU_MMX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 127 },
    { 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0}, 0, 2, 5 },
    { 0, CPU_SSE2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0}, 0, 2, 22 }
};

static const x86_insn_info sseps_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 5 }
};

static const x86_insn_info cvt_rx_xmm32_insn[] = {
    { SUF_L, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 129 },
    { SUF_L, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 247 },
    { SUF_Q, CPU_64, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 135 },
    { SUF_Q, CPU_64, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 249 }
};

static const x86_insn_info cvt_mm_xmm64_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 207 },
    { 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 209 }
};

static const x86_insn_info cvt_xmm_mm_ps_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 221 }
};

static const x86_insn_info cvt_xmm_rmx_insn[] = {
    { SUF_L, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 120 },
    { SUF_Q, CPU_64, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 162 }
};

static const x86_insn_info ssess_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 5 }
};

static const x86_insn_info ssecmpps_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_Imm8, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 5 }
};

static const x86_insn_info ssecmpss_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 5 }
};

static const x86_insn_info ssepsimm_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 29 }
};

static const x86_insn_info ssessimm_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 3, 29 }
};

static const x86_insn_info ldstmxcsr_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 0, 1, 66 }
};

static const x86_insn_info maskmovq_insn[] = {
    { 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xF7, 0}, 0, 2, 459 }
};

static const x86_insn_info movaups_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 5 },
    { 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 14 }
};

static const x86_insn_info movhllhps_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 0 }
};

static const x86_insn_info movhlps_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 25 },
    { 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 46 }
};

static const x86_insn_info movmskps_insn[] = {
    { SUF_L, CPU_386, CPU_SSE, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x50, 0}, 0, 2, 129 },
    { SUF_Q, CPU_64, CPU_SSE, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x50, 0}, 0, 2, 135 }
};

static const x86_insn_info movntps_insn[] = {
    { 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x2B, 0}, 0, 2, 343 }
};

static const x86_insn_info movntq_insn[] = {
    { 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xE7, 0}, 0, 2, 251 }
};

static const x86_insn_info movss_insn[] = {
    { 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x10, 0}, 0, 2, 0 },
    { 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x10, 0}, 0, 2, 65 },
    { 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x11, 0}, 0, 2, 74 }
};

static const x86_insn_info pextrw_insn[] = {
    { SUF_L, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 126 },
    { SUF_L, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 129 },
    { SUF_Q, CPU_64, CPU_MMX, CPU_P3, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 132 },
    { SUF_Q, CPU_64, CPU_SSE2, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 135 },
    { 0, CPU_SSE41, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x15}, 0, 3, 138 },
    { 0, CPU_386, CPU_SSE41, 0, {0, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x15}, 0, 3, 141 },
    { 0, CPU_64, CPU_SSE41, 0, {0, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x15}, 0, 3, 144 }
};

static const x86_insn_info pinsrw_insn[] = {
    { SUF_L, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 102 },
    { SUF_Q, CPU_64, CPU_MMX, CPU_P3, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 105 },
    { SUF_L, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 108 },
    { SUF_L, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 111 },
    { SUF_Q, CPU_64, CPU_SSE2, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 114 },
    { SUF_L, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 117 }
};

static const x86_insn_info pmovmskb_insn[] = {
    { SUF_L, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 126 },
    { SUF_L, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 129 },
    { SUF_Q, CPU_64, CPU_MMX, CPU_P3, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 132 },
    { SUF_Q, CPU_64, CPU_SSE2, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 135 }
};

static const x86_insn_info pshufw_insn[] = {
    { 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x70, 0}, 0, 3, 159 }
};

static const x86_insn_info cvt_xmm_xmm64_ss_insn[] = {
    { 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 0 },
    { 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 25 }
};

static const x86_insn_info cvt_xmm_xmm64_ps_insn[] = {
    { 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 0 },
    { 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 25 }
};

static const x86_insn_info cvt_rx_xmm64_insn[] = {
    { SUF_L, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 129 },
    { SUF_L, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 226 },
    { SUF_Q, CPU_64, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 135 },
    { SUF_Q, CPU_64, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 375 }
};

static const x86_insn_info cvt_mm_xmm_insn[] = {
    { 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 445 }
};

static const x86_insn_info cvt_xmm_mm_ss_insn[] = {
    { 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 221 }
};

static const x86_insn_info movaupd_insn[] = {
    { 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0}, 0, 2, 5 },
    { 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x01, 0}, 0, 2, 14 }
};

static const x86_insn_info movhlpd_insn[] = {
    { 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0}, 0, 2, 25 },
    { 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x01, 0}, 0, 2, 46 }
};

static const x86_insn_info movmskpd_insn[] = {
    { SUF_L, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x50, 0}, 0, 2, 129 },
    { SUF_Q, CPU_64, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x50, 0}, 0, 2, 135 }
};

static const x86_insn_info movntpddq_insn[] = {
    { 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0}, 0, 2, 343 }
};

static const x86_insn_info vmxmemrd_insn[] = {
    { SUF_L, CPU_Not64, CPU_P4, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 171 },
    { SUF_Q, CPU_64, CPU_P4, 0, {0, 0, 0}, 64, 64, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 177 }
};

static const x86_insn_info vmxmemwr_insn[] = {
    { SUF_L, CPU_Not64, CPU_P4, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 87 },
    { SUF_Q, CPU_64, CPU_P4, 0, {0, 0, 0}, 64, 64, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 90 }
};

static const x86_insn_info vmxtwobytemem_insn[] = {
    { 0, CPU_P4, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 0, 1, 26 }
};

static const x86_insn_info vmxthreebytemem_insn[] = {
    { 0, CPU_P4, 0, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 26 }
};

static const x86_insn_info cvt_xmm_xmm32_insn[] = {
    { 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 0 },
    { 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 65 }
};

static const x86_insn_info maskmovdqu_insn[] = {
    { 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xF7, 0}, 0, 2, 0 }
};

static const x86_insn_info movdqau_insn[] = {
    { 0, CPU_SSE2, 0, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 5 },
    { 0, CPU_SSE2, 0, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 14 }
};

static const x86_insn_info movdq2q_insn[] = {
    { 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 207 }
};

static const x86_insn_info movq2dq_insn[] = {
    { 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 333 }
};

static const x86_insn_info pslrldq_insn[] = {
    { 0, CPU_SSE2, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x73, 0}, 0, 2, 22 }
};

static const x86_insn_info lddqu_insn[] = {
    { 0, CPU_SSE3, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0xF0, 0}, 0, 2, 457 }
};

static const x86_insn_info ssse3_insn[] = {
    { 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 159 },
    { 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 5 }
};

static const x86_insn_info ssse3imm_insn[] = {
    { 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 159 },
    { 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 29 }
};

static const x86_insn_info sse4_insn[] = {
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 5 }
};

static const x86_insn_info sse4imm_insn[] = {
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 29 }
};

static const x86_insn_info sse4m32imm_insn[] = {
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 21 },
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 65 }
};

static const x86_insn_info sse4m64imm_insn[] = {
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 21 },
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 25 }
};

static const x86_insn_info sse4xmm0_insn[] = {
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 5 },
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 156 }
};

static const x86_insn_info crc32_insn[] = {
    { SUF_B, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 379 },
    { SUF_W, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 16, 0, 0xF2, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 381 },
    { SUF_L, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 32, 0, 0xF2, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 87 },
    { SUF_B, CPU_64, CPU_SSE42, 0, {0, 0, 0}, 64, 0, 0xF2, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 383 },
    { SUF_Q, CPU_64, CPU_SSE42, 0, {0, 0, 0}, 64, 0, 0xF2, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 90 }
};

static const x86_insn_info extractps_insn[] = {
    { 0, CPU_386, CPU_SSE41, 0, {0, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x17}, 0, 3, 150 },
    { 0, CPU_64, CPU_SSE41, 0, {0, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x17}, 0, 3, 144 }
};

static const x86_insn_info insertps_insn[] = {
    { 0, CPU_SSE41, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x21}, 0, 3, 65 },
    { 0, CPU_SSE41, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x21}, 0, 3, 21 }
};

static const x86_insn_info movntdqa_insn[] = {
    { 0, CPU_SSE41, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x2A}, 0, 2, 427 }
};

static const x86_insn_info sse4pcmpstr_insn[] = {
    { 0, CPU_SSE42, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 29 }
};

static const x86_insn_info pextrb_insn[] = {
    { 0, CPU_SSE41, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x14}, 0, 3, 153 },
    { 0, CPU_386, CPU_SSE41, 0, {0, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x14}, 0, 3, 141 },
    { 0, CPU_64, CPU_SSE41, 0, {0, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x14}, 0, 3, 144 }
};

static const x86_insn_info pextrd_insn[] = {
    { 0, CPU_386, CPU_SSE41, 0, {0, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x16}, 0, 3, 150 }
};

static const x86_insn_info pextrq_insn[] = {
    { 0, CPU_64, CPU_SSE41, 0, {0, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x16}, 0, 3, 147 }
};

static const x86_insn_info pinsrb_insn[] = {
    { 0, CPU_SSE41, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x20}, 0, 3, 123 },
    { 0, CPU_386, CPU_SSE41, 0, {0, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x20}, 0, 3, 111 }
};

static const x86_insn_info pinsrd_insn[] = {
    { 0, CPU_386, CPU_SSE41, 0, {0, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x22}, 0, 3, 120 }
};

static const x86_insn_info pinsrq_insn[] = {
    { 0, CPU_64, CPU_SSE41, 0, {0, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x22}, 0, 3, 162 }
};

static const x86_insn_info sse4m16_insn[] = {
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 117 },
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 0 }
};

static const x86_insn_info sse4m32_insn[] = {
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 65 },
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 0 }
};

static const x86_insn_info sse4m64_insn[] = {
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 25 },
    { 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 0 }
};

static const x86_insn_info cnt_insn[] = {
    { SUF_W, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0xF3, 0, 2, {0x0F, 0x00, 0}, 0, 2, 84 },
    { SUF_L, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0xF3, 0, 2, {0x0F, 0x00, 0}, 0, 2, 87 },
    { SUF_Q, CPU_64, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0xF3, 0, 2, {0x0F, 0x00, 0}, 0, 2, 90 }
};

static const x86_insn_info extrq_insn[] = {
    { 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x78, 0}, 0, 3, 1 },
    { 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x79, 0}, 0, 2, 0 }
};

static const x86_insn_info insertq_insn[] = {
    { 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x78, 0}, 0, 4, 0 },
    { 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x79, 0}, 0, 2, 0 }
};

static const x86_insn_info movntsd_insn[] = {
    { 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x2B, 0}, 0, 2, 46 }
};

static const x86_insn_info movntss_insn[] = {
    { 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x2B, 0}, 0, 2, 74 }
};

static const x86_insn_info sse5com_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 4, 28 }
};

static const x86_insn_info sse5com32_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 4, 20 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 4, 64 }
};

static const x86_insn_info sse5com64_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 4, 20 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 4, 24 }
};

static const x86_insn_info cvtph2ps_insn[] = {
    { 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x30}, 0, 2, 0 },
    { 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x30}, 0, 2, 25 }
};

static const x86_insn_info cvtps2ph_insn[] = {
    { 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x31}, 0, 2, 42 },
    { 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x31}, 0, 2, 46 }
};

static const x86_insn_info sse5arith_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 8 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x00}, 0, 4, 12 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x04}, 0, 4, 4 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x04}, 0, 4, 16 }
};

static const x86_insn_info sse5arith32_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 32 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 68 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x00}, 0, 4, 40 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x00}, 0, 4, 72 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x04}, 0, 4, 48 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x04}, 0, 4, 76 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x04}, 0, 4, 56 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x04}, 0, 4, 80 }
};

static const x86_insn_info sse5arith64_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 32 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 36 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x00}, 0, 4, 40 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x00}, 0, 4, 44 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x04}, 0, 4, 48 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x04}, 0, 4, 52 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x04}, 0, 4, 56 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x04}, 0, 4, 60 }
};

static const x86_insn_info sse5two_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00}, 0, 2, 5 }
};

static const x86_insn_info sse5two32_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00}, 0, 2, 0 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00}, 0, 2, 65 }
};

static const x86_insn_info sse5two64_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00}, 0, 2, 0 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00}, 0, 2, 25 }
};

static const x86_insn_info sse5pmacs_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 4 }
};

static const x86_insn_info sse5prot_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x40}, 0, 3, 4 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x40}, 0, 3, 16 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7B, 0x40}, 0, 3, 29 }
};

static const x86_insn_info sse5psh_insn[] = {
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x44}, 0, 3, 4 },
    { 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x44}, 0, 3, 16 }
};

static const x86_insn_info now3d_insn[] = {
    { 0, CPU_3DNow, 0, 0, {MOD_Imm8, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0, 2, 159 }
};

static const x86_insn_info cmpxchg16b_insn[] = {
    { 0, CPU_64, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 343 }
};

static const x86_insn_info invlpga_insn[] = {
    { 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 0, 0 },
    { 0, CPU_386, CPU_SVM, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 2, 357 }
};

static const x86_insn_info skinit_insn[] = {
    { 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 0, 0 },
    { 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 1, 484 }
};

static const x86_insn_info svm_rax_insn[] = {
    { 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 0, 0 },
    { 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 1, 357 }
};

static const x86_insn_info padlock_insn[] = {
    { 0, CPU_PadLock, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_Op1Add}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 0, 0 }
};

static const x86_insn_info cyrixmmx_insn[] = {
    { 0, CPU_Cyrix, CPU_MMX, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 159 }
};

static const x86_insn_info pmachriw_insn[] = {
    { 0, CPU_Cyrix, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x5E, 0}, 0, 2, 209 }
};

static const x86_insn_info rdwrshr_insn[] = {
    { 0, CPU_686, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x36, 0}, 0, 1, 88 }
};

static const x86_insn_info rsdc_insn[] = {
    { 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 377 }
};

static const x86_insn_info cyrixsmm_insn[] = {
    { 0, CPU_486, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 378 }
};

static const x86_insn_info svdc_insn[] = {
    { 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 449 }
};

static const x86_insn_info ibts_insn[] = {
    { 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 165 },
    { 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 171 }
};

static const x86_insn_info umov_insn[] = {
    { 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x10, 0}, 0, 2, 211 },
    { 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 165 },
    { 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 171 },
    { 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x12, 0}, 0, 2, 213 },
    { 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 84 },
    { 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 87 }
};

static const x86_insn_info xbts_insn[] = {
    { 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 373 },
    { 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 247 }
};